Manufacturing method for metal oxide semiconductor field effect transistor

Abstract

The invention discloses a manufacturing method for a metal oxide semiconductor field effect transistor. The manufacturing method comprises the steps of forming a gate structure and inner-offset spacers on an SOI substrate; forming first raised source-drain regions on the two sides of the inner-offset spacers; forming first outer spacers on the two sides of the inner-offset spacers higher than the first raised source-drain regions; continuously forming second raised source-drain regions on the first raised source-drain regions on the two sides of the first outer spacers; and continuously forming second outer spacers on the two sides of the first outer spacers higher than the second raised source-drain regions. By forming the low-stray-capacitance and fully-depleted type silicon-on-insulator metal oxide semiconductor field effect transistor with the stepped spacer structure, the resistance and stray capacitance in a source-drain expansion region can be balanced; the stray capacitance between the raised source-drain regions and the gate electrodes can be reduced while it is ensured that the impurity distribution in the source-drain expansion region is not changed; and in addition, the manufacturing method has the advantages of simple process, low cost and the like, and can be applicable to substrates of different crystal orientations.

Description

technical field [0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and more specifically, relates to the manufacture of a fully depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with a stepped sidewall structure and low parasitic capacitance method. Background technique [0002] In modern integrated circuit technology, using raised source-drain regions (RSD) as source and drain is an effective way to improve transistor performance. RSD can reduce the source-drain resistance, and the combination of RSD and in-situ doping technology can be used to form ultra-shallow junctions, which can effectively reduce the junction capacitance at the source-drain. In FDSOI, since the silicon layer in the source and drain regions is very thin, in order to reduce the resistance, RSD is almost a necessary technology. The main problem of RSD is that it is isolated from the gate only by o...

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Problems solved by technology

However, this method requires a sloped notch at the bottom of its final exterior wall structure to balance the trade-off between resistance and parasitic capacitance

Moreover, when using this method to grow sacrificial raised source and drain regions with inclined sidewalls, there are special requirements for the crystal orientation of semiconductor-on-insulator, and the requirements for surface cleanliness are also high; at the same time, the introduction of sacrificial raised source and drain regions The process is also more complex

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