Method of fabricating semiconductor structure

A technology of conductor structure and gate structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., and can solve the problems of increasing the complexity of the integrated circuit manufacturing process.

Active Publication Date: 2017-06-09
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this kind of miniaturization process also increases the complexity of the integrated circuit manufacturing process

Method used

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  • Method of fabricating semiconductor structure
  • Method of fabricating semiconductor structure
  • Method of fabricating semiconductor structure

Examples

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Embodiment Construction

[0012] The following disclosure provides numerous different embodiments or examples for implementing different features of the subject matter provided herein. Specific examples of components and arrangements are described below to simplify the present disclosure. Such components and arrangements are of course examples only and are not intended to be limiting. For example, in the description below, the formation of a first feature on or over a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which the first feature is formed in direct contact with the second feature. Embodiments where additional features are formed between second features such that the first and second features are not in direct contact. In addition, the present invention may repeat element symbols and / or letters in various examples. This repetition is for purposes of simplicity and clarity, and does not ...

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PUM

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Abstract

The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.

Description

technical field [0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor structure. Background technique [0002] Semiconductor integrated circuits (integrated circuits, ICs) have experienced rapid growth. In the course of development, the functional density of semiconductor devices has increased while device feature sizes or geometries have decreased. Scaling downprocess generally provides benefits by increasing production efficiency, reducing cost, and / or improving device performance. However, such a miniaturization process also increases the complexity of the integrated circuit manufacturing process. [0003] In deep sub-micron integrated circuit technology, non-volatile memory devices have become popular storage units due to various advantages. Specifically, the data stored in the non-volatile memory device will not be lost when the power is turned off. One particular example of a non-volatile memory device includes a floating ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66409H01L29/78H01L29/6656H01L29/40114H01L21/31116H01L29/66825H01L21/3065H01L21/76829H01L21/76841H01L29/6684H01L29/788H10B41/30H01L29/6653
Inventor 廖耕颍陈柏仁陈怡傑陈益弘
Owner TAIWAN SEMICON MFG CO LTD
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