Detection circuit and detection method of look-up tables in FPGA chip

Abstract

The invention provides a detection circuit and detection method of look-up tables in an FPGA chip. The FPGA chip comprises N configurable logic blocks. Each of the configurable logic blocks comprises two sections with M look-up tables, wherein one section is a detected circuit, and the other section is the detection circuit. The detection circuit comprises a control signal circuit which sends a control signal, multiple selectors which receive the control signal and connect the look-up tables of an equal level in the detected circuit, or connect an SR_IN port or triggers of an upper level, a clock signal circuit which sends a clock signal, and multiple triggers which receive the clock signal and is connected to the selector of an equal level in the detection circuit, wherein a trigger of a lowest level is connected to an SR_OUT port. The detection circuit and detection method has the advantages of a fast running speed, time sequence convergence, and a stable and reliable test result.

Description

technical field [0001] The invention relates to the field of integrated circuit chip testing, in particular to a detection circuit and a detection method of a look-up table in an SRAM FPGA chip. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. [0003] Xilinx 7 series FPGA includes Artix-7, Kentix-7 and Virtex-7 three subclasses. The configurable logic block (CLB) structure of the three types of devices is the same, such as figure 1 shown. Each CLB consists of 2 slices, and each slice has a unique physical location number (such as X0Y0, X2Y1). [0004] A Look Up Table (LUT) is a functional module that implements programmable combinational logic in a slice, such as figure 2 As shown, the lookup table in the 7 series FPGA adopts the LUT6 structure, and there are 6 input ports (I0~I5) and 2 output ports (O5, O6). Eac...

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Problems solved by technology

The advantage of this method is that it is relatively simple in design and implementation, and does not need to write complex physical constraint codes; the disadvantage is that it is impossible to accurately locate and analyze the detected faults physically

[0010] In addition, some test methods are considered from the application level. The general idea is to establish test auxiliary circuits and interconnection structures based on other resources inside the FPGA, and to test specific functions of LUTs or other resources with external excitation signals. These methods are generally Fault coverage is not considered

[0011] Finally, the test objects of the existing test methods are generally traditional LUT4 units, so most of the test structures are established based on the CLB architecture of Virtex, Virtex-2 and Virtex-4 FPGAs, and there is a lack of LUT6, especially 7 Research on LUT6 Test Method in CLB of Serial FPGA

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