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Throughput test method of gpu FFMA instruction in dual-issue mode

A test method and dual-launch technology, applied in instrumentation, design optimization/simulation, calculation, etc., can solve problems such as unpublished parameters and closed GPU architecture, and achieve the effect of optimized application

Active Publication Date: 2019-07-30
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to solve the situation that the existing GPU architecture is closed and many parameters are not announced, and provide a micro-benchmark test method for accurately detecting GPU parameters

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  • Throughput test method of gpu FFMA instruction in dual-issue mode
  • Throughput test method of gpu FFMA instruction in dual-issue mode
  • Throughput test method of gpu FFMA instruction in dual-issue mode

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Embodiment Construction

[0027]The present invention provides a method for testing the throughput of GPU FFMA instructions in a dual-launch mode, wherein the test method includes an instruction delay / flux test step, a register bank test step, a control code meaning test step, and an FFMA double-launch flux test steps, where:

[0028] The instruction delay / flux test step is responsible for testing the delay and throughput of the GPU instruction, obtaining the delay cycle and the GPU instruction flux of the GPU instruction, and sending the delay cycle and the GPU instruction flux of the GPU instruction to the controller code meaning test steps;

[0029] The register bank test step, according to judging whether there is a bank conflict between the registers, selects the register operand without bank conflict, and sends the register operand to the FFMA double emission flux test step;

[0030] The control code meaning test step is to analyze and test the meaning of the control code in the GPU command thro...

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Abstract

The invention relates to a flux test method for a GPU FFMA instruction in a dual-emitting mode. The flux test method comprises the following steps: testing the delay and the flux of a GPU instruction to acquire the delay period and the flux of the GUP instruction; selecting a register operand free of bank collision according to the fact that whether bank collision exists between registers or not; and analyzing and testing the meaning of a control code in the GPU instruction according to the delay period and the flux of the GPU instruction, controlling to start a corresponding emitting mode and thread scheduling of a GPU according to the meaning of the control code, and if the started emitting mode is the dual-emitting mode, calculating and testing the flux of a GPU float-point multiply-add instruction in the dual-emitting mode according to the dual-emitting mode and the register operand. Parameters of the GPU and the corresponding relationship between the parameters and the performance of the GPU are tested through a micro benchmark test program to obtain the relationship between the parameters and the performance, and application to the GPU is favorably optimized.

Description

technical field [0001] The invention relates to the technical fields of GPU microarchitecture and compiler code generation, and in particular to a flux testing method of a GPU FFMA instruction (floating-point multiply-add instruction) in a dual-issue mode. Background technique [0002] The characteristics and parameters of the microarchitecture are an important reference and basis for all architecture-related optimizations. However, many architectural characteristics and parameters that have an important impact on performance are not disclosed. For this reason, the present invention uses GPU (Graphics Processing Unit) assembly language to design micro-benchmarks (micro-benchmarks) to detect and expose these architectural features and parameters. In particular, during the optimization process of the matrix multiplication algorithm, the architectural features and parameters that the present invention focuses on include: instruction read-after-write dependency delay, instructio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/20G06F30/398
Inventor 张秀霞谭光明王朝尉
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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