A clock distribution device for digitizing pet detectors

Abstract

A clock distribution apparatus for a digital PET detector, comprising at least one clock module (10), wherein each clock module (10) comprises: an active crystal oscillator (11), which is used for generating a clock signal; a phase-locked loop (12) which is in communication connection with the active crystal oscillator (11), the phase-locked loop (12) processing a clock signal and generating a first differential signal; a first clock fan-out buffer (13), which is respectively connected to the phase-locked loop (12) and in communication connection with a twelve-channel output connector (70); an FPGA chip (30), which is in communication connection with the twelve-channel output connector (70), the FPGA chip (30) sending a second low-voltage differential signal generated thereby to the output connector (70); a sliding switch (20), which is connected to the FPGA chip (30) so as to optionally send a relatively high or low level; a light touch switch (40), which is connected to the FPGA chip (30) so as to send a reset signal; and an input connector (50), which is connected to the FPGA chip (30) and a second clock fan-out buffer (60). The present apparatus can provide at least twelve channels of synchronous clock signals and synchronous reset signals, and clock modules (10) can be cascaded into a tree structure for providing more outputs; and the apparatus has strong applicability.

Description

technical field [0001] The invention relates to a femtosecond clock distribution device in the field of medical imaging, more particularly to a clock distribution device for digitized PET detectors. Background technique [0002] PET (Positron Emission Tomography, Positron Emission Tomography) imaging technology is a relatively advanced clinical examination imaging technology in the field of nuclear medicine. More and more hospitals have begun to use clinical PET machines for auxiliary diagnosis and treatment. In PET imaging technology, the ideal clock signal is a periodic square wave with a certain amplitude and frequency, which is used to drive various electronic chips containing sequential logic, such as ARM (Acorn RISC Machine) processors, FPGAs and CPUs, etc. , the measurement unit of the frequency of the clock signal adopts the SI unit hertz (Hz). The reset signal refers to a period of high or low level, which is used to reset the sequential logic. For the digital PET ...

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a clock distribution device for digitized PET detectors, thereby solving the problem that a sufficient number of synchronous clock signals or reset signals cannot be provided in the prior art

Images