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A data cell array structure of nand flash memory and its manufacturing method

A data unit and array structure technology, applied in electrical components, semiconductor devices, circuits, etc., can solve the problem of data unit read interference, etc., and achieve the effects of small off current, good process size and continuous reduction capability, and fast switching speed.

Active Publication Date: 2019-08-16
SHANGHAI FUDAN MICROELECTRONICS GROUP
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Problems solved by technology

[0009] The invention provides a data unit array structure of NAND flash memory and a manufacturing method thereof, which has a good capability of continuously shrinking the process size and solves the problem of reading interference of data units

Method used

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  • A data cell array structure of nand flash memory and its manufacturing method
  • A data cell array structure of nand flash memory and its manufacturing method
  • A data cell array structure of nand flash memory and its manufacturing method

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Embodiment Construction

[0119] based on the following Figure 3 ~ Figure 15 , specifically explain the preferred embodiment of the present invention.

[0120] The invention provides a data unit array structure of NAND flash memory. The data unit array structure of NAND flash memory is manufactured by adopting fin field effect transistor technology, and the data unit is a tunneling field effect transistor (TFET).

[0121]TFET is a simple P-I-N diode with gate control, which is a diode that works under reverse bias conditions. The working mechanism of a MOSFET depends on whether the carriers flow in the channel, but a TFET uses the band-to-band tunneling current as its working mechanism. In the OFF state, the potential barrier between source and channel is wide, no BTBT occurs, and only very small leakage current exists. However, when the gate voltage exceeds the threshold voltage, the potential barrier between the channel and the source becomes narrow enough to allow a large tunnel current to flow, ...

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Abstract

A data unit array structure and its manufacturing method of NAND flash memory forms the fin part on the semiconductor substrate.The polar layer is formed on the fins of the fins. The layer structure includes the tunnel penetration medium layer covering the top of the fins and the top of the tunnel medium layer on the top of the tunnel, the top of the charged trap layer and the charged trap layer, and the charged trap layer and the charging trap layer and the charging trap layer and the charging trap layer.The mass layer on both sides and the top of the grid medium layer and the grid on both sides, one end of the finish part of the fins forms the string source, and forms the other end of the fins.String leak.The present invention has a good process size that continues to shrink and solves the problem of reading interference.The data unit uses TFET, which is a dual -gate device with fast switching speed and small off current.The formation method of the data unit is compatible with the traditional FinFET process, which simplifies the process and reduces the cost of process.

Description

technical field [0001] The invention relates to a data unit array structure of NAND flash memory and a manufacturing method thereof, in particular to a method for manufacturing the data unit array structure of NAND flash memory by using a Fin Field Effect Transistor process and the obtained TFET data unit array structure. Background technique [0002] NAND flash is a non-volatile flash memory technology developed by Toshiba Corporation. It has a high cell density, can achieve high storage density, and has fast writing and erasing speeds. The unit size of NAND flash is almost half of that of NOR devices, which can provide higher capacity within a given die size, has fast writing and erasing speeds, and its main function is to store data. It is currently mainly used in digital camera flash memory card and MP3 player. [0003] Such as figure 1 As shown, the existing NAND flash memory includes a channel region 1 located on a semiconductor substrate, a tunnel dielectric layer 2...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11517H01L27/11521H10B41/00H10B41/30
CPCH10B69/00
Inventor 黄新运肖磊沈晔晖沈磊刘岐刘红霞
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP
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