Random validation method for making random constraints be selectively driven by coverage rate

A random verification and coverage technology, applied in the field of random verification, can solve problems such as reducing engineers, and achieve the effect of reducing time consumption

Active Publication Date: 2017-10-20
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The technical task of the present invention is to provide a coverage-driven random verification method with optional random constraints to solve the problem of how to implement random verification based on coverage-driven random constraints that can be dynamically evaluated and selected, so as to realize the random verification process Dynamic adjustment of random constraints in , and reduce the workload of engineers

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  • Random validation method for making random constraints be selectively driven by coverage rate
  • Random validation method for making random constraints be selectively driven by coverage rate
  • Random validation method for making random constraints be selectively driven by coverage rate

Examples

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Embodiment 1

[0067] as attached figure 1 As shown, the optional random verification method based on coverage-driven random constraints of the present invention includes the following steps:

[0068] (1) Clearly define all required random constraints in the random verification environment, and define the value range of the above random constraints;

[0069] (2) Divide the random constraints defined in step (1) into multiple groups of random constraint combinations, and set the simulation order of the above multiple groups of random constraint combinations, wherein there is no actual functional completeness between each two groups of random constraint combinations In the case of overlap, for example, in a system where there are only two nodes, and the interface of each node can only send at most two requests in one clock cycle, the random constraint a limits the node to send only one request per clock cycle, and the random constraint b limits A node only receives one request per clock cycle...

Embodiment 2

[0085] as attached image 3 As shown, this embodiment is a further improvement on the basis of Embodiment 1. The difference between this embodiment and Embodiment 1 is: in a simulation process, all required random constraint combinations are simulated and verified in random order. This embodiment The difference between embodiment and embodiment 1 is specifically:

[0086]In step (2), the random constraints defined in step (1) are divided into multiple groups of random constraint combinations, and there is no complete overlap of actual functions between each group of random constraint combinations, for example, there are only two nodes, In a system where the interface of each node can only send at most two requests in one clock cycle, the random constraint a restricts the node to send only one request per clock cycle, and the random constraint b restricts the node to receive only one request per clock cycle, then These two constraints are actually equivalent in this system, an...

Embodiment 3

[0098] Embodiment 1 performs simulation verification on all required random constraint combinations in one simulation process, but when the number of random constraint combinations is large, traversing all random constraint combinations through one simulation process is relatively inefficient. In view of the above problems, this embodiment has been further improved on the basis of embodiment 1, as attached Figure 5 As shown, the difference between this embodiment and embodiment 1 is specifically:

[0099] In step (2), the random constraints defined in step (1) are divided into multiple groups of random constraint combinations, and there is no complete overlap of actual functions between each group of random constraint combinations, for example, there are only two nodes, In a system where the interface of each node can only send at most two requests in one clock cycle, the random constraint a restricts the node to send only one request per clock cycle, and the random constrain...

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Abstract

The invention discloses a random validation method for making random constraints be selectively driven by a coverage rate, belongs to the field of random validation, and aims at solving the technical problem how to achieve random validation in which the random constraints can be subjected to dynamic evaluation and is selectively driven by the coverage rate. The method includes the steps of (1) defining all random constraints needed in a random validation environment, and defining value ranges of the random constraints above; (2) dividing all defined random constraint combinations in need into multiple groups of random constraint combinations, wherein the actual functions of every two groups of the random constraint combinations are not completely overlapped; (3) setting a coverage rate counting period capable of being dynamically adjusted; (4) during the coverage rate counting period, counting increase situation of the coverage rate in the current emulated validation process, adding the newly increased coverage rate into existing coverage rate data, and using the increase situation of the coverage rate in the current emulated validation process as an evaluation criterion to conduct emulated validation on the random constraint combinations above.

Description

technical field [0001] The invention relates to the field of random verification, in particular to a random verification method based on coverage drive with optional random constraints. Background technique [0002] With the continuous development of process technology and application fields, the complexity of chips continues to increase. Correspondingly, the requirements for simulation verification work are also increasing. getting stricter. [0003] The existing chip design process is divided into two stages: front-end design (logical design) and back-end design (physical design). The front-end design is mainly to realize the logic function of the chip through the hardware description language (such as verilog), and the correctness of the code description is mainly realized through the simulation verification of these codes (or the netlist generated by these codes). In the standard simulation verification process, the function points of the logic functions involved in th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/20
Inventor 李拓
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD
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