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Fan-out package structure and preparation method thereof

A packaging structure, fan-out technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as damage to electronic components, cracking of semiconductor chips, and affecting the handling of semiconductor equipment, so as to avoid warping, Avoid the effect of cracking

Inactive Publication Date: 2017-10-27
SJ SEMICON JIANGYIN CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a fan-out packaging structure and its preparation method, which are used to solve the problem caused by the warping of the fan-out wafer-level packaging structure in the prior art. Issues that affect the handling of semiconductor equipment for subsequent processes and that lead to cracking of semiconductor chips or damage to electronic components inside package structures

Method used

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  • Fan-out package structure and preparation method thereof
  • Fan-out package structure and preparation method thereof

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Embodiment 1

[0062] see figure 1 , this embodiment provides a method for preparing a fan-out packaging structure, the method for preparing a fan-out packaging structure includes the following steps:

[0063] 1) providing a substrate;

[0064] 2) forming a semiconductor chip on the upper surface of the substrate;

[0065] 3) forming a first plastic packaging material layer on the upper surface of the substrate, the first plastic packaging material layer fills the gap between the semiconductor chips, and encapsulates the semiconductor chips;

[0066] 4) forming a second molding material layer on the upper surface of the first molding material layer, wherein the second molding material layer and the first molding material layer are molding material layers of different materials;

[0067] 5) removing the substrate;

[0068] 6) forming a rewiring layer on the surface of the first molding material layer away from the second molding material layer, and the rewiring layer is electrically connec...

Embodiment 2

[0110] read on Figure 9 , this embodiment also provides a fan-out packaging structure, the fan-out packaging structure is prepared by the preparation method described in the first embodiment, the fan-out packaging structure includes: a rewiring layer 16, the The rewiring layer 16 includes opposite first surfaces and second surfaces; the semiconductor chip 13 is located on the first surface of the rewiring layer 16 and is electrically connected to the rewiring layer 16; the first plastic encapsulation material Layer 14, the first molding material layer 14 is located on the first surface of the rewiring layer 16, the first molding material layer 14 fills the gaps between the semiconductor chips 13, and the semiconductor chips 13 encapsulating plastic packaging; the second plastic packaging material layer 15, the second plastic packaging material layer 15 is located on the surface of the first plastic packaging material layer 14 away from the rewiring layer 16, the second plasti...

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Abstract

The invention provides a fan-out packaging structure and a preparation method thereof. The fan-out packaging structure includes: a rewiring layer; a semiconductor chip located on the first surface of the rewiring layer; a first plastic packaging material layer located on the rewiring layer the first surface of the first plastic encapsulation material layer, located on the surface of the first plastic encapsulation material layer away from the rewiring layer; solder bumps, located on the second surface of the rewiring layer. The fan-out packaging structure of the present invention can effectively release the thermal stress caused by thermal expansion or contraction by forming two layers of plastic packaging material layers of different materials, thereby effectively avoiding the warping of the fan-out packaging structure and further avoiding its internal The cracking of the semiconductor chip will not affect the processing of the fan-out packaging structure in the subsequent process.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging structure and a preparation method thereof. Background technique [0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size. Currently, advanced packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip, Package on Package (Package on Package, POP) and so on. [0003] Fan-out wafer-level packaging is an embedded chip packaging method for wafer-level processing. It is currently one of the advanced packaging methods with more input / output ports (I / O) and better integration flexibility. Compared with conventional wafer-level packaging, fan-out wafer-level pack...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/48H01L23/488H01L21/56H01L21/60H01L23/29
CPCH01L21/568H01L2224/04105H01L2224/12105H01L2224/19H01L2224/96H01L2924/3511H01L23/3114H01L21/563H01L23/293H01L23/3121H01L24/11H01L2224/02331H01L2224/02379H01L2224/02381
Inventor 陈彦亨林正忠
Owner SJ SEMICON JIANGYIN CORP
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