Tcl/ Tk script-based method for repairing clock tree fan-out default

Abstract

The invention discloses a Tcl / Tk script-based method for repairing clock tree fan-out default. The method comprises the following steps of inputting three parameters, namely the full name of a fan-out default pin, the name of an inserted buffer, whether or not the method is executed for the first time; traversing all fan-out units connected to the fan-out default pin, and dividing all the fan-out units into two groups evenly; disconnecting time sequence ports of all the fan-out units from the fan-out default pin; grasping the name of the level corresponding to each fan-out unit, and creating new buffers and connection lines which are needed to be added at the corresponding level; according to a principle of no change in the logic relation of a circuit, connecting the two groups of fan-out units with the output ends of the two buffers respectively, and connecting the input ends of the two buffers to the default pin respectively. According to the Tcl / Tk script-based method for repairing the clock tree fan-out default, the clock tree fan-out default can be repaired quickly, the time of logic constraint and convergence is shortened, the manual operation is reduced, and the reliability and efficiency of digital physical design are improved.

Description

technical field [0001] The invention belongs to the technical field of digital physical design in semiconductor integrated circuits, and in particular relates to the physical design of SoC (System on Chip, System on Chip) with high operating frequency and fast speed, which realizes the rapid repair of fan-out violation of clock tree logic and physical constraints, This approach can also be applied to quick fixes for fanout violations during the routing phase. Background technique [0002] Clock tree synthesis is the core of digital physical design. The clock signal transmitted by the clock tree drives the work of the entire system, and the logical constraint violations on the clock tree must be cleaned up. When performing clock tree synthesis, you first need to set logical constraints, such as fan-out, transition time, and load capacitance. Fan-out convergence is an important goal of logic convergence. If the fan-out is too large, it will be difficult for the previous-level...

AI Technical Summary

Problems solved by technology

Fan-out convergence is an important goal of logic convergence. If the fan-out is too large, it will be difficult for the previous-level registers to drive the subsequent-level registers, so that the timing of this level cannot be accurately obtained through the process library, affecting the accuracy of setup time and hold time. Make the circuit not work accurately according to the clock beat

Existing digital physical design software such as ICC (IC Compiler) can solve most fan-out problems, but because physical design software needs to consider many factors when performing layout and routing, such as blocking positions, standard cell congestion, timing issues, etc., There are more or less fan-out violations that are hard to fix

[0003] One of the usual solutions at this time is manual repair, but if the number of defaults is too large, manual repair is too inefficient and error-prone; the other method is to use ECO (Engineering Change Order, engineering modification) tools, but ECO The price of tools is very expensive. For example, the ECO tool of a domestic company costs at least 200,000 to 300,000 RMB, and the user interface is not very friendly, and it takes a long time to initialize the ECO tool. The script exported by the ECO tool will eventually have to To execute with digital physical software, due to the correlation problem between different softwares, multiple rounds of interaction between ECO tools and digital physical design software are required to completely solve the problem

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