Optoelectronic chip package and optoelectronic chip packaging process
A photoelectric chip and packaging process technology, which is applied in photovoltaic power generation, circuits, electrical components, etc., can solve the problems of insufficient process margin, difficulty in precise control of laser energy, and low light-emitting efficiency and light-receiving efficiency of photoelectric components, so as to improve packaging quality. rate effect
Inactive Publication Date: 2017-11-07
CHIPMOS TECH INC
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Problems solved by technology
[0004] However, because the encapsulant is too thick and the energy of the laser is not easy to control accurately, forming contact openings in the encapsulant by laser drilling faces the problem of insufficient process window.
Therefore, laser drilling may cause damage to the optoelectronic element, which in turn leads to problems such as low light extraction efficiency or light collection efficiency of the optoelectronic element.
Accordingly, laser drilling may cause the packaging yield of optoelectronic components to not be effectively improved
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[0041] Figure 1A to Figure 1C It is a schematic diagram of the manufacturing process of an optoelectronic chip package according to an embodiment of the present invention. First, please refer to Figure 1A , providing a circuit carrier 210 with an existing optoelectronic chip 220, wherein the optoelectronic chip 220 has a light guide element 230 thereon, and the circuit carrier 210 has a first surface 210a and a second surface 210b. Specifically, the circuit carrier 210 includes a core layer 212, a conductor C, a first pad 212a, a second pad 212b, a first solder resist layer 214a and a second solder resist layer 214b, wherein the core layer 212 is hard or Flexible dielectric material, the first pad 212a and the second pad 212b are respectively located on two opposite surfaces S1, S2 of the core layer 212, and the first pad 212a is respectively connected to the conductor embedded in the core layer 212 C is electrically connected to the corresponding second pad 212b. The firs...
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The invention relates to an optoelectronic chip package and an optoelectronic chip packaging process. The optoelectronic chip package comprises a line carrier, a photoelectric chip, a light-guiding component and an encapsulant, wherein the photoelectric chip is disposed on the line carrier and electrically connected to the line carrier. The light guiding component is disposed on the optoelectronic chip. The encapsulant is disposed on the line carrier, wherein the encapsulant encapsulates the optoelectronic chip and the light guiding component, and a top surface of the light guiding component is exposed outside the encapsulant. A manufacturing process for manufacturing the optoelectronic chip package has also been proposed. This process sequence can help improve the package yield of the optoelectronic chip packaging process.
Description
technical field [0001] The present invention relates to a photoelectric chip packaging body and a photoelectric chip packaging process, and in particular to a photoelectric chip packaging body with a light guide element and a photoelectric chip packaging process. Background technique [0002] In the semiconductor industry, the production of integrated circuits (Integrated Circuits, IC) is mainly divided into three stages: the manufacture of wafers, the manufacture of integrated circuits, and the packaging of chips. Among them, the chip is completed through the steps of wafer fabrication, circuit design, photomask fabrication, circuit fabrication, and wafer dicing. After the electrical connection, the chip can be covered with encapsulation colloid material. The purpose of the encapsulation is to prevent the chip from being affected by moisture, heat, and noise, and to provide a medium for electrical connection between the chip and the external circuit, thus completing the int...
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IPC IPC(8): H01L31/048H01L31/054
CPCY02E10/52H01L31/048H01L31/054
Inventor 陈宪章翁承谊黄东鸿
Owner CHIPMOS TECH INC