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Integrated circuit layout data processing task allocation method and device and cluster system

A technology for layout data and processing tasks, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems that affect cluster parallel acceleration ratio and efficiency, large time difference, and calculation time difference, etc., to reduce communication The overhead and time difference are small, and the effect of improving the parallel acceleration ratio and efficiency

Active Publication Date: 2017-11-14
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, such a task allocation method is too simple, because the number of polygons contained in each task unit (that is, each column) is generally different, resulting in a difference in the calculation time for each task unit, if the polygon in the original layout data The distribution is uneven, then there will be some columns containing a large number of polygons, and some columns are few, so the time for different processes to complete tasks will vary greatly, thus affecting the parallel speedup and efficiency of the entire cluster

Method used

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  • Integrated circuit layout data processing task allocation method and device and cluster system
  • Integrated circuit layout data processing task allocation method and device and cluster system
  • Integrated circuit layout data processing task allocation method and device and cluster system

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Embodiment

[0045] see figure 1 , figure 1 It is a flow chart of a method for allocating integrated circuit layout data processing tasks provided by an embodiment of the present invention. This method is applied to cluster systems such as figure 1 shown, including:

[0046] Step S101, read the layout data file, and determine each column;

[0047] Specifically, the layout data file is read row by row, and each column is determined.

[0048] Step S102, recording the number of polygons contained in each column, and calculating the total number of polygons from the number of polygons contained in each column;

[0049] Step S103, calculating the average number of pre-allocated polygons for each sub-process based on the total number of polygons and the number of sub-processes of the cluster system;

[0050] Specifically, divide the total number of polygons by the number of sub-processes to obtain the average number of pre-allocated polygons for each sub-process. Optionally, if the quotien...

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Abstract

The invention discloses an integrated circuit layout data processing task allocation method and device and a cluster system. The method comprises the following steps: reading a layout data file, and determining various columns; recording the number of polygons contained in each column, and calculating the total number of all the polygons according to the number of the polygons contained in each column; calculating the number of averagely pre-allocated polygons of each subprocess according to the total number of all the polygons and the number of subprocesses of the cluster system; dividing the various columns into continuous task blocks with a set number according to a preset rule, so that the sum of an absolute value of a difference between the number of the polygons in each task block and the corresponding number of averagely pre-allocated polygons is minimum, and the set number and the number of the subprocesses are equal; allocating the various task blocks to the various subprocesses according to a one-one mapping way. By applying the technical scheme provided by the invention, a parallel speed-up ratio and efficiency of the cluster system can be effectively improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit layout design, in particular to a method, device and cluster system for allocating integrated circuit layout data processing tasks. Background technique [0002] In the process of CMP (Chemical Mechanical Polishing, chemical mechanical polishing) model simulation for integrated circuit layout, how to extract accurate layout characteristic parameters is a key factor affecting the CMP model simulation. Compared with the traditional serial computing method on a single computer for layout feature parameter extraction, parallel calculation of the most time-consuming grid feature parameters in layout feature parameter extraction through computer clusters can not only speed up the extraction of the entire layout feature parameters , improve the utilization of idle resources, and has the advantages of high cost performance, high availability, high flexibility and good scalability. With the con...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/392G06F2111/02
Inventor 黄天怡陈岚张贺曹鹤
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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