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Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as the reduction of electrical performance of semiconductor devices, and achieve the effect of optimizing electrical performance and avoiding losses

Active Publication Date: 2020-03-10
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the shallow trench isolation structure of the prior art is likely to cause the reduction of the electrical performance of the semiconductor device

Method used

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  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof

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Experimental program
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Embodiment Construction

[0031] It can be seen from the background art that the shallow trench isolation structure in the prior art is likely to cause the reduction of the electrical performance of the semiconductor device, and the reason is analyzed in combination with the manufacturing method of the semiconductor structure in the prior art. combined reference Figure 1 to Figure 6 , which shows a schematic structural diagram corresponding to each step in an embodiment of a method for manufacturing a semiconductor structure in the prior art.

[0032] refer to figure 1 , providing a base (not marked), the base includes a substrate 100 and a fin 110 protruding from the substrate 100 , and the substrate includes a first region I and a second region II.

[0033] In this embodiment, the substrate is used to form an SRAM, the first region I is used to form a pull-down (PD, PullDown) transistor or a transfer gate (PG, Pass Gate) transistor, and the second region II is used to form an upper Pull (PU, Pull...

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PUM

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Abstract

A semiconductor structure and a manufacturing method thereof, the method comprising: providing a base, the base includes a substrate, and fins protruding from the substrate, the substrate includes a first region and a second region; forming a first region on the substrate An initial isolation layer; patterning the first initial isolation layer, forming a first opening exposing the substrate at the junction of the first region and the second region; forming a sidewall protection of a material different from that of the substrate and the fin on the sidewall of the first opening layer; etch the substrate along the first opening to form a second opening in the substrate; form a second initial isolation layer filling the second opening and the first opening; remove part of the thickness of the second initial isolation layer, sidewall protection layer and the first initial isolation layer, exposing the fins. In the present invention, the first opening is firstly formed in the first initial isolation layer, and then the side wall protection layer is formed on the side wall of the first opening, and then the substrate is etched along the first opening. The sidewall protection layer can protect the fins on both sides of the first opening, so as to prevent the process of etching the substrate from causing loss to the fins.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] With the development trend of high-density integrated circuits, the devices that make up the circuit are placed more closely in the chip to fit the available space of the chip. Correspondingly, the density of active devices per unit area of ​​the semiconductor substrate continues to increase, so effective insulation between devices becomes more important. [0003] Shallow Trench Isolation (STI) technology has a good isolation effect (for example: process isolation effect and electrical isolation effect), shallow trench isolation technology also has the ability to reduce the area occupied by the wafer surface and increase the integration of devices Etc. Therefore, with the reduction of the size of integrated circuits, the isolation between devices is now mainly using shallow trench isolation...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/8244H01L27/11H10B10/00
CPCH01L21/76224H10B10/12
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP