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Scheduler device and method for dynamic loop-to-processor mapping

A technology for scheduling equipment and number of cycles, applied in the field of multi-parallel computing, can solve problems such as infeasibility and high computing time, achieve the effect of minimum power consumption limit, solve optimization problems, and reduce user workload

Active Publication Date: 2017-11-28
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But these methods involve high computation time and are not feasible in a scheduling environment due to the large overhead involved

Method used

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  • Scheduler device and method for dynamic loop-to-processor mapping
  • Scheduler device and method for dynamic loop-to-processor mapping
  • Scheduler device and method for dynamic loop-to-processor mapping

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Embodiment Construction

[0062] In the drawings, the same reference symbols denote the same or equivalent elements. Additionally, it should be noted that not all figures are drawn to scale.

[0063] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

[0064] Apparently, the described embodiments are only some embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

[0065] figure 1 An example of a conventional program structure is shown.

[0066] Each program may consist of a series of blocks 101, 103, 105, 107, 109, such as figure 1 shown in . The first block 101 and the last block 109 are sequential blocks, but all other intermediate blocks 103,...

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Abstract

A scheduler device and a method for mapping program blocks to cores of a heterogeneous multi-core system, comprising at least two types of cores, c1, c2, the method comprising the steps of: estimating (S1), in run-time, available resources of the heterogeneous multi-core system for parallel execution of at least one program block; determining (S2) a first number of loops, n1, and a second number of loops, n2, of the program block, to be associated with each of the at least two types of cores of the heterogeneous multi-core system, wherein a total number of loops, N=n1+n2, of the program block is to be executed in the heterogeneous multi-core system on the estimated available resources; checking (S3) a power consumption condition, and if the power consumption condition is not satisfied, modifying a clock frequency, f1 of the first type, c1 cores and determining again the first, n1, and the second, n2, number of loops to be associated with each of the at least two types, c1, c2, of cores; and parallel executing (S4) the determined first number, n1, of loops on the available cores of the first type, c1, and the determined second number, n2, of loops on the available cores of the second type, c2, of the heterogeneous multi-core system.

Description

technical field [0001] The present disclosure relates to the field of multi-parallel computing in a computer architecture mainly in the form of a multi-core processor for a multi-core computing system, in particular, to a scheduling device and a multi-core and many-core heterogeneous computing system Dynamic Cycle-Adaptive Performance and Power Scheduling Methods for Processor Mapping. Background technique [0002] Multi-core and many-core heterogeneous computing systems (MMCHCS) are recently widely used in networked mobile systems, such as mobile phones, PDAs, and even small notebook computers. [0003] These systems contain two types of processor cores: common cores, which are expected to run efficiently, and low-power cores, which are expected to be used for power-aware operation. The second type of core allows cutting off the energy consumption of the computing system when possible. This also results in reduced power consumption of the computing system, allowing for ex...

Claims

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Application Information

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IPC IPC(8): G06F9/48G06F9/50
CPCG06F9/4893G06F9/5094Y02D10/00
Inventor 米哈伊尔·彼得罗维奇·莱文
Owner HUAWEI TECH CO LTD
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