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A SDR-based method for generating digitally modulated signals with arbitrary code rates

A digital modulation signal and code rate technology, which is applied in various modulation transmitter/receiver arrangements, digital transmission systems, modulation carrier systems, etc., can solve channel imbalance, inability to miniaturize equipment, inability to generate high-quality signals, etc. problems, to achieve stable performance, facilitate implementation, and reduce costs

Active Publication Date: 2019-06-14
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0004] The traditional method of generating arbitrary code rate signals adopts the method of transforming the sampling clock. In addition to the signal processing chip, an external clock chip, multi-chip DAC (or a multi-channel DAC) and analog up-conversion chip are required, resulting in the inability to miniaturize the device; the generated The code rate of the modulated signal cannot be continuously adjusted arbitrarily, which makes it unsuitable for testing and application scenarios of all code rate signals; in its hardware architecture, the baseband signal needs to be output by a multi-channel DAC and simulated by quadrature up-conversion to obtain an intermediate frequency signal. The unbalance between and the inaccuracy of the analog quadrature carrier phase difference lead to the inability to produce a high-quality signal

Method used

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  • A SDR-based method for generating digitally modulated signals with arbitrary code rates
  • A SDR-based method for generating digitally modulated signals with arbitrary code rates
  • A SDR-based method for generating digitally modulated signals with arbitrary code rates

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Embodiment 1

[0062] This embodiment describes a flow chart of a method for generating a digitally modulated signal with an arbitrary code rate based on SDR in a specific implementation of the present invention.

[0063] figure 1 It is a composition circuit schematic diagram of a pseudo-random sequence generator that parallelizes the LFSR structure of the pseudo-random sequence generator in the method of the present invention;

[0064] figure 2 It is a parallel design for parallelizing the LFSR structure of the pseudo-random sequence generator in A of the method step 1 of the present invention.

[0065] image 3 It is a system composition and method flow chart based on the SDR-based arbitrary code rate digital modulation signal generation method of the present invention.

[0066] from image 3 It can be seen that after the j channel data is generated, it enters the convolution module through data storage, and the selection of the data address is calculated by the address update module ...

Embodiment 2

[0068] In Embodiment 2, an example of sending an 8PSK signal with a code rate of 100 Mbps is used to describe the specific implementation process of the present invention.

[0069] Step A, firstly generate an 8-bit PN code as an information flow, map it according to the design requirements, store it in RAM, and update the value in RAM according to the data request information.

[0070] Step B, generate 6 look-up tables, the depth of each look-up table is 1024, represented by 12bit, and stored in the tap coefficient of the shaping filter;

[0071] Step C, calculate the phase control word of each channel code DDS according to the code rate, sampling rate, system processing clock, channel number and channel serial number. In this embodiment, the code rate Rs is 100 Mbps, the sampling rate Fs is 5 GHz, the system processing clock F1 is 156.25 Mhz, the number of channels M is 32, and m is 32.

[0072] Can be based on Calculate the channel phase.

[0073] Step D, according to Ph...

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Abstract

The present invention relates to an SDR-based arbitrary bit rate digitally modulated signal generating method, belonging to the technical field of communication signal processing. The present invention uses a FPGA and a single-channel DAC hardware architecture, and utilizes the frequency-dividing clock of a fixed sampling clock as a system processing clock parallel multi-channel signal generated at each clock according to the code rate, the sampling clock, the number of parallel channels and channel values Selecting a filter tap coefficient in a designed look-up table and performing shaping filtering operation with a high bit rate data stream; finally, the multi-channel parallel signal undergoes digital up-conversion and parallel-serial conversion to obtain a code rate arbitrary settable intermediate frequency digital signal , Through the DAC output to the balun issued an analog signal. Compared with the traditional conversion sampling clock method, the hardware structure is simpler, the performance is more stable, the invention is better and the modularization is higher.

Description

technical field [0001] The invention relates to an SDR-based arbitrary code rate digital modulation signal generation method, which belongs to the technical field of communication signal processing. Background technique [0002] With the fierce competition in the field of aerospace in the world, high-speed data transmission systems suitable for user spacecraft such as satellite communications and UAV data links have become the key development direction of countries in the world. A device with powerful functions, high degree of modularization, and strong versatility, which can be used as a test device or a payload of an arbitrary code rate modulation signal, is particularly important. [0003] The SDR (software defined radio)-based method for generating a digital modulation signal with an arbitrary code rate is a key technology in a device for generating a signal with an arbitrary code rate modulation. This method supports all amplitude-phase joint modulation methods includi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04B1/00H04L27/00
CPCH04B1/0003H04L27/0008
Inventor 王帅方金辉宋哲刘子尧
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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