Tunneling transistor and method for fabricating the same

Abstract

Provided are a tunnelling transistor and a tunnelling transistor manufacturing method. The tunnelling transistor comprises a substrate (10), a first source electrode region (50), a drain electrode region (60), a second source electrode region (80), a channel (90), a halo ring layer (100), a gate dielectric layer (20) and a gate electrode region (30). The first source electrode region (50) and the drain electrode region (60) are formed on the substrate (10). The second source electrode region (80) is formed between the first source electrode region (50) and the drain electrode region (60), so that the channel (90) is formed between the second source electrode region (80) and the drain electrode region (60). The halo ring layer (100) is formed on a part of the surface of the second source electrode region (80). The gate dielectric layer (20) and the gate electrode region (30) are successively formed on the halo ring layer (100). Also provided is a tunnelling transistor manufacturing method. By using a line tunnelling mechanism, the tunnelling probability of a tunnelling transistor is improved, thereby increasing a tunnelling current of the tunnelling transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a tunneling transistor and a method for preparing the tunneling transistor. Background technique [0002] Microelectronic devices are generally fabricated on semiconductor substrates and then integrated circuits. A Complementary Metal Oxide Semiconductor (CMOS) is a core unit of an integrated circuit, and its size follows Moore's law to obtain better performance, higher integration density and lower cost. [0003] However, as the dimensions of CMOS transistors shrink, their power consumption continues to increase. This is partly due to the increase in leakage current caused by short-channel effects, but also due to the difficulty in scaling down the supply voltage of CMOS devices. Among them, it is difficult to reduce the power supply voltage of CMOS devices mainly because the subthreshold swing SS is limited, and it cannot be lower than 60mV / decade at room temperature. ...

AI Technical Summary

Problems solved by technology

Due to the small tunneling area of ​​the point tunneling mechanism, the gate-controlled electric field of the tunneling junction is not strong, resulting in a low probability of carrier tunneling, which makes TFET have the disadvantage of small tunneling current.

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