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Semiconductor device, manufacturing method thereof and electronic device

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve problems that affect device performance, critical dimensions fail to meet design requirements, etc., and achieve the effect of improving performance

Active Publication Date: 2017-12-15
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, when fabricating NAND flash memory, wet processes after contact hole (CT) etching, such as photoresist removal, etch residue removal, cleaning, etc., will have an important impact on critical dimensions and profiles. impact, making the bottom key dimensions such as the drain contact not meet the design requirements, which in turn affects the performance of the final device

Method used

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  • Semiconductor device, manufacturing method thereof and electronic device
  • Semiconductor device, manufacturing method thereof and electronic device
  • Semiconductor device, manufacturing method thereof and electronic device

Examples

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Embodiment 1

[0062] The following will refer to image 3 as well as Figure 4A to Figure 4H A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.

[0063] First, step 301 is performed to provide a semiconductor substrate 400, the semiconductor substrate 400 includes a core region 400A and a peripheral region 400B, an active region is formed in the core region 400A and a peripheral region 400B, and is located between the active regions The gate stack 401 on the top and the interlayer dielectric layer covering the active region and the gate stack, the formed structure is as follows Figure 4A shown.

[0064] Wherein, the semiconductor substrate 400 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors composed of these semiconductors. The layer structure or the like may be silicon-on-insulator...

Embodiment 2

[0107] The present invention also provides a semiconductor device, such as Figure 5 As shown, the semiconductor device includes: a semiconductor substrate 500, the semiconductor substrate 500 includes a core area 500A and a peripheral area 500B, and both the core area 500A and the peripheral area 500B include an active area, located in the active area The gate stack 501 above and the interlayer dielectric layer covering the active region and the gate stack 501, and the first contact hole 504 above the active region, wherein the interlayer The dielectric layer includes an initial interlayer dielectric layer (ILD0) 502 between the gate stacks and a first interlayer dielectric layer (ILD1) 503 above the initial interlayer dielectric layer, so A protection layer 505 is formed on the sidewall of the first contact hole 504 .

[0108] Wherein the semiconductor substrate 500 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / ...

Embodiment 3

[0118] Still another embodiment of the present invention provides an electronic device, including the above-mentioned semiconductor device and an electronic component connected to the semiconductor device. Wherein, the semiconductor device includes: a semiconductor substrate, the semiconductor substrate includes a core area and a peripheral area, and the core area and the peripheral area each include an active area, a gate stack located on the active area and an interlayer dielectric layer covering the active region and the gate stack, and a first contact hole above the active region, wherein a protective layer is formed on the sidewall of the first contact hole layer.

[0119] The semiconductor substrate can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors etc. or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-g...

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Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The manufacturing method comprises the steps of: providing a semiconductor substrate, wherein the semiconductor substrate comprises a core region and a peripheral region, and active regions, gate stacks positioned on the active regions and an interlayer dielectric layer covering the active regions and the gate stacks are formed in the core region and the peripheral region, forming first contact holes positioned in the active regions; forming a protective layer on the sidewall of each first contact hole; and forming second contact holes positioned in the gate stacks. According to the manufacturing method, the protective layers are formed on the sidewalls of the first contact holes, so that critical dimensions and sections of the first contact holes in the subsequent process are not liable to change under the action of a wet process, thereby being conductive to improving performance of the device. The semiconductor device has critical dimensions and the sections of the contact holes in the active regions which conform to design requirements, thereby being conductive to improving the performance of the semiconductor device. The electronic device has similar advantages.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] NAND (NAND) flash memory has become the mainstream non-volatile storage technology and is widely used in various fields such as data centers, personal computers, mobile phones, smart terminals, and consumer electronics, and the demand is still growing. As the NAND flash memory (flash memory) enters the technology node of 24nm and below, the critical dimension of the drain contact in the NAND flash memory shrinks accordingly. For 2X˜1X (for example, 24nm˜14nm) NAND flash memory, the etch process of the drain contact is very challenging due to the large aspect ratio. The bottom critical dimension of the drain contact needs to be small enough to be able to sit above the active area. Additionally, the device profile must be tungsten (W) void-fill friendly. ...

Claims

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Application Information

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IPC IPC(8): H01L27/11529H01L21/768
CPCH01L21/768H01L2027/11861H10B69/00H10B41/20H10B41/30
Inventor 张翼英常荣耀洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP