Packaging structure for integration of image sensor chip and logic chip and packaging method for integration of image sensor chip and logic chip

A technology for image sensors and logic chips, which is applied in the fields of electric solid-state devices, semiconductor devices, radiation control devices, etc., can solve the problems of large packaging volume, low device stability, and low product yield, and achieve small packaging volume and reliable devices high performance and improved packaging performance

Inactive Publication Date: 2017-12-22
SJ SEMICON JIANGYIN CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a packaging structure and packaging method for an integrated image sens

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  • Packaging structure for integration of image sensor chip and logic chip and packaging method for integration of image sensor chip and logic chip
  • Packaging structure for integration of image sensor chip and logic chip and packaging method for integration of image sensor chip and logic chip
  • Packaging structure for integration of image sensor chip and logic chip and packaging method for integration of image sensor chip and logic chip

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[0044] The following describes the implementation of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See Figure 1~Figure 10 . It should be noted that the diagrams provided in this embodiment only illustrate the basic idea of ​​the present invention in a schematic way, so the diagrams only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation. For size drawing, the type, quantity, and proportion of each component can be changed at will during actual imple...

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Abstract

The present invention provides a packaging structure for integration of an image sensor chip and a logic chip and a packaging method for integration of an image sensor chip and a logic chip. The packaging structure comprises: a rewiring layer; a transparent cover plate packaged at the first surface of the rewiring layer; a metal lead structure protruded on the second surface of the rewiring layer; an image sensor chip and a logic chip are arranged on the second surface of the rewiring layer, wherein the image sensor chip, the logic chip and the metal lead structure are electrically connected to each other through the rewiring layer; and packaging materials formed on the second surface of the rewiring layer. The image sensor chip and the logic chip are integrated in a same packaging chamber, the packaging size is small, and the reliability of a device is high; and moreover, and a metal column made in advance is employed to realize electrical leading out of the rewiring layer so as to greatly save the technology cost with no need for technologies such through-silicon via, etc.

Description

technical field [0001] The invention belongs to the field of semiconductor packaging, in particular to a packaging structure and packaging method for an integrated image sensor chip and a logic chip. Background technique [0002] With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density. [0003] Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a An im...

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Application Information

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IPC IPC(8): H01L23/538H01L27/146H01L21/56
CPCH01L21/568H01L23/5389H01L27/146H01L2224/04105H01L2224/19H01L2224/24137H01L2224/96
Inventor 陈彦亨林正忠何志宏
Owner SJ SEMICON JIANGYIN CORP
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