Chip package structure and package method

Abstract

The invention relates to the technical field of chip package, and discloses a chip package method. The chip package method comprises the steps of providing a carrying plate; positively arranging a plurality of chips on the carrying plate; electrically connecting adjacent chips by a bonding wire; packaging the chips and the bonding wires to form a plastic package body by a plastic package process,and allowing the bonding wires to be at least partially exposed; and forming a conductor layer on a region, where the bonding wires are exposed, of a surface of the plastic package body. By the chip package method, a wire rack of a metal material is not needed to be fabricated in advance, the cost is reduced, the fabrication process of the wire rack is saved, the process of arranging the wire rackunder the chips is omitted, the package process is effectively simplified, the package difficulty is reduced, the package efficiency is improved, the problem that the wire rack is deformed caused byprocesses such as surface mounting and bonding during the traditional package process is prevented, and the product yield is remarkably improved.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a packaging method. Background technique [0002] QFN (Quad Flat No-lead Package), is one of the surface mount packages, because of its good electrical and thermal performance, small size and light weight, it has been more and more widely used Applications. Generally, the QFN package structure is square or rectangular. There is a large-area exposed pad for heat conduction at the center of the bottom of the package, and there are conductive pads for electrical connection on the periphery of the package surrounding the large pad. [0003] The prior art discloses a QFN packaging structure, which includes a lead frame structure, a semiconductor chip and a packaging unit. The lead frame structure includes a base, a plurality of terminals and a first metal layer, and the base has a central area for To carry a semiconductor chip, and a peripheral ...

AI Technical Summary

Problems solved by technology

[0004] The above-mentioned QFN packaging structure has the following defects: 1. A lead frame structure needs to be formed before packaging, and the preparation cost of the lead frame structure is relatively high, and the process is relatively complicated; 2. The lead frame structure is located at the bottom of the chip, and the overall package thickness is relatively large, and It is not conducive to the heat dissipation at the bottom of the chip; 3. When packaging the chip, each contact electrode of each chip needs to be connected to the lead frame frame, which consumes a lot of manpower and time costs; 4. In the patch or wire bonding process It is easy to cause problems such as deformation of the lead frame frame, which affects the yield of the overall packaged chip

Images