Packaging method of back-illuminated cmos sensor

A CMOS sensor and packaging method technology, applied in radiation control devices and other directions, can solve the problems of low device stability, low product yield, and large packaging volume of image sensor chips and logic chips, so as to improve packaging performance and save process costs. , the effect of high sensing performance and device reliability
CN107611152BActive Publication Date: 2020-02-04SJ SEMICON JIANGYIN CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SJ SEMICON JIANGYIN CORP
Publication Date
2020-02-04

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Abstract

The invention provides a method for packaging a backside illuminated CMOS sensor, which comprises a re-wiring layer, a backside illuminated CMOS sensor structure fixedly connected to the second surface of the re-wiring layer, a logic chip arranged on the first surface of the re-wiring layer, a packaging material coated on the logic chip, a through hole formed in the packaging material, and a metallead structure formed in the through hole so as to realize the electrical lead out of the re-wiring layer, the backside illuminated CMOS sensor structure and the logic chip. According to the invention, the backside illuminated CMOS sensor, the logic chip and the metal lead structure are electrically connected through the method of the re-wiring layer, so that the packaging backside illuminated CMOS sensor is small in packaging size, high in sensing performance and high in device reliability. The electrical lead out of the re-wiring layer can be realized only by manufacturing metal columns inthe packaging materials in advance, so that the processes of silicon perforation and the like are not needed. The process cost can be greatly saved.
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Description

technical field

[0001] The invention belongs to the field of semiconductor packaging, in particular to a packaging method for a back-illuminated CMOS sensor. Background technique

[0002] With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density.

[0003] Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a An important packaging method for high-demand m...

Claims

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