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Lithography alignment method for three-dimensional integration process

A technology of lithography alignment and three-dimensional integration, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc. The effect of poor accuracy and improved accuracy

Inactive Publication Date: 2018-01-26
上海微阱电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to overcome the above-mentioned defects existing in the prior art, and provide a lithography alignment method for three-dimensional integration process to solve the weak and unstable lithography alignment signal existing in the existing three-dimensional integrated circuit process technical problem

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  • Lithography alignment method for three-dimensional integration process
  • Lithography alignment method for three-dimensional integration process
  • Lithography alignment method for three-dimensional integration process

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Embodiment Construction

[0025] The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0026] It should be noted that, in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly show the structure of the present invention for the convenience of description, the structures in the drawings are not drawn according to the general scale, and are drawn Partial magnification, deformation and simplification are included, therefore, it should be avoided to be interpreted as a limitation of the present invention.

[0027] In the following specific embodiments of the present invention, please refer to figure 1 , figure 1 It is a flow chart of a photolithographic alignment method for three-dimensional integration process of the present invention; meanwhile, please refer to Figure 2-Figure 7 , Figure 2-Figure 7 is the basis of a preferred embodiment of the pr...

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Abstract

The invention discloses a lithography alignment method for the three-dimensional integration process. A deep groove stretching into an internal portion of a top-layer wafer is etched at the front surface of the top-layer wafer, dielectric layer filling into the groove is carried out to form a lithography alignment mark, so the lithography alignment mark can be clearly identified after the back side thinning process of the top-layer wafer is accomplished, and lithography alignment of the wafer back side process can be accurately carried out. The method is advantaged in that problems of alignment incapability and poor alignment precision caused by weak and unstable alignment mark signals existing in the top-layer wafer front-end process in the prior art are solved, and lithography alignmentprecision of the three-dimensional integration process is improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and more particularly, to a photolithography alignment method used in a three-dimensional integration process. Background technique [0002] In the current manufacturing process of semiconductor manufacturing devices, a complete chip generally has to go through at least ten to twenty times of photolithography. In order to make the semiconductor device work normally, the layers of each photolithography process must be registered within a certain range of accuracy; except for the first photolithography, the photolithography of the remaining layers must have the layers of the layer before exposure. Graphics are aligned with graphics left over from previous layers. The process of photolithography alignment exists in the process of plate loading and wafer exposure, and its purpose is to cover the patterns on the photolithography plate with the maximum pr...

Claims

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Application Information

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IPC IPC(8): H01L21/68H01L23/544
Inventor 卢意飞
Owner 上海微阱电子科技有限公司