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Binary network realization system for recognition of common speech words

A binary network and system realization technology, applied in the field of artificial neural network, can solve the problems of high power consumption and large network scale.

Active Publication Date: 2018-02-02
SOUTHEAST UNIV
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Problems solved by technology

[0005] Purpose of the invention: In order to solve the problems of large network scale and excessive power consumption in the existing neural network used in speech recognition, the present invention provides a binary network implementation system for recognition of common speech words, which is applied to keyword speech recognition, Convolutional Neural Network Binarization and Approximate Adder Design

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  • Binary network realization system for recognition of common speech words
  • Binary network realization system for recognition of common speech words
  • Binary network realization system for recognition of common speech words

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Embodiment Construction

[0019] Below in conjunction with specific embodiment, further illustrate the present invention, should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various equivalent forms of the present invention All modifications fall within the scope defined by the appended claims of the present application.

[0020] The implementation system of the binary network oriented to speech common words recognition is to convert the multiplication and addition of the input data in the binary network and the weight of binarization into an operation of XOR and inverter chain delay. Among them, the XOR multiplier converts the multiplication operation into the XOR of the flag bit of the data and the binary weight, and the digital-analog mixed vector matrix summation module based on the delay of the inverter chain co...

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Abstract

The invention discloses a binary network realization system for recognition of common speech words. Common speech words are recognized using a binary convolution network. The circuit structure includes an Exclusive OR multiplier, a digital-analog hybrid vector matrix summing module, and a counting quantification based on a mixed clock frequency. The system is applied to keyword speech recognition,convolution neural network binaryzation and approximate adder design. The system not only can reduce the power consumption and time produced by calculation, but also can ensure the calculation precision to a certain degree and simplify the complexity of calculation.

Description

technical field [0001] The invention relates to a binary network realization system oriented to speech common words recognition, and belongs to the technical field of artificial neural networks. Background technique [0002] With the increasing size of the network, the research on network compression and proper processing precision in terms of software model and hardware architecture is getting more and more in-depth. Although recurrent neural networks generally used for speech recognition have relatively high accuracy, there are problems in reducing area and energy consumption. Therefore, a binary convolutional network with high energy efficiency is introduced, which trades little accuracy loss for lower energy consumption. [0003] Delay-based approximate adders show superior performance and flexibility when dealing with binary networks. With the increasing influence of neural networks, research on speech recognition of common words with low power consumption is imminent...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04
CPCG06N3/045
Inventor 刘波秦海孙锰阳郑梦瑶龚宇杨军
Owner SOUTHEAST UNIV
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