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Self-alignment dual composition method, semiconductor device and manufacturing method therefor, and electronic apparatus

A semiconductor, self-aligned technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical solid-state devices, etc., can solve problems such as load effects, and achieve good yield and performance, less dents, and consistent pattern density.

Active Publication Date: 2018-02-16
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, due to the different pattern density of the memory array and the peripheral area, there is also a serious loading effect between the memory array and the peripheral area during gate etching

Method used

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  • Self-alignment dual composition method, semiconductor device and manufacturing method therefor, and electronic apparatus
  • Self-alignment dual composition method, semiconductor device and manufacturing method therefor, and electronic apparatus
  • Self-alignment dual composition method, semiconductor device and manufacturing method therefor, and electronic apparatus

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Embodiment 1

[0042] The following will refer to Figure 4A ~ Figure 4I A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.

[0043] First, if Figure 4A As shown, a semiconductor substrate 400 is provided. The semiconductor substrate 400 includes a storage region 400A and a peripheral region 400B. A gate stack is formed on the storage region 400A and a peripheral region 400B. The gate stack includes a tunneling Oxide layer (not shown), floating gate material layer 401, gate dielectric layer 402 and control gate material layer 403, a first hard mask layer 404, a second hard mask layer are formed on the gate stack layer 405 and patterned sacrificial layer 406.

[0044] Wherein, the semiconductor substrate 400 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors composed of these semiconducto...

Embodiment 2

[0079] The present invention also provides a semiconductor device fabricated by the above method, such as Figure 5 As shown, the semiconductor device includes: a semiconductor substrate 500, the semiconductor substrate 500 includes a storage area 500A and a peripheral area 500B, a word line WL and a selection gate SG are formed on the storage area 500A, and in the peripheral area 500B is formed with a logic gate Gate, a source and a drain, wherein the word line includes a word line WL for programming and a dummy word line WL' adjacent to the selection gate SG, and the word line for programming The spacing between WL is the same as the spacing between the dummy word line WL' and the select gate SG.

[0080] Wherein the semiconductor substrate 500 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multilayers composed of these semiconductors The structure or the like may be s...

Embodiment 3

[0085] Still another embodiment of the present invention provides an electronic device, including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, the semiconductor device includes: a semiconductor substrate, the semiconductor substrate includes a storage area and a peripheral area, a word line and a selection gate are formed on the storage area, a logic gate, a source electrode are formed on the peripheral area and a drain, wherein the word lines include a word line for programming and a dummy word line adjacent to the select gate, and the spacing between the word lines for programming is the same as that of the dummy word line and the select gate. The spacing between the grids is the same.

[0086] The semiconductor substrate can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors e...

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Abstract

The invention provides a self-alignment dual composition method, a semiconductor device and a manufacturing method therefor, and an electronic apparatus. According to the manufacturing method, a novelself-alignment dual composition method is adopted to manufacture a word line, so that etching windows of a selection gate are increased, and etching dents caused by an etching load effect can be avoided. The performance and the yield of the semiconductor device and the electronic apparatus are improved by virtue of the manufacturing method.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a self-aligned double patterning method, a semiconductor device and a manufacturing method thereof, and an electronic device. Background technique [0002] With the development of semiconductor manufacturing technology, flash memory (flash memory) with faster access speed has been developed in terms of storage devices. Flash memory has the characteristics that information can be stored, read, and erased multiple times, and the stored information will not disappear after power failure. Therefore, flash memory has become a popular choice for personal computers and electronic devices. A widely used type of non-volatile memory. However, NAND (NAND gate) fast memory is widely used in fields with high read / write requirements due to its large storage capacity and relatively high performance. Recently, the capacity of NAND flash memory chips has reached 2GB, and the size is rapi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/033H01L21/8234H01L21/8239H01L27/11529H10B41/41H10B99/00
CPCH01L21/0338H01L21/8234H01L2223/54426H10B99/00H10B41/35
Inventor 黄永彬杨海玩周乾
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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