Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Dual-side SiP three-dimensional package structure

A three-dimensional packaging and packaging structure technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of difficult balance of various materials, complex packaging, warping deformation, etc., to reduce chip loss and improve high frequency. The effect of performance, high yield

Active Publication Date: 2018-03-06
JCET GROUP CO LTD
View PDF8 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, with the high-density circuits in the packaging process, the use of various packaging materials, and the use of various chips and functional devices, the entire package is very complicated, and the matching of various materials is not easy to balance, which may easily lead to overall warping and deformation.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Dual-side SiP three-dimensional package structure
  • Dual-side SiP three-dimensional package structure
  • Dual-side SiP three-dimensional package structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] see figure 1 , a double-sided SiP three-dimensional packaging structure in this embodiment, which includes a core interposer 1, and the front side of the core interposer 1 is mounted with a fan-out wafer-level packaging structure 2 and a first passive component 3 , the fan-out wafer level packaging structure 2 and the first passive element 3 are provided with a first 3D conductive component 4, and the fan-out wafer level packaging structure 2, the first passive element 3 and the first 3D conductive The component 4 is encapsulated with a first molding compound 5, the front of the first 3D conductive component 4 is exposed to the first molding compound 5, and a chip 7 and a second passive component 8 are mounted on the back of the core adapter board 1, and the chip 7 A second 3D conductive component 6 is arranged on the periphery of the second passive component 8, and the chip 7, the second passive component 8 and the second 3D conductive component 6 are encapsulated with...

Embodiment 2

[0043] see figure 2 , the difference between embodiment 2 and embodiment 1 is: a first substrate 11 is arranged under the package structure, the package structure is connected to the front of the first substrate 11 through the first metal ball 10, and the back of the first substrate 11 Second solder balls 12 are provided, and underfill glue 13 is provided between the packaging structure and the first substrate 11 .

Embodiment 3

[0045] join image 3 , a double-sided SiP three-dimensional packaging structure in this embodiment, which includes a core interposer 1, and the front side of the core interposer 1 is mounted with a fan-out wafer-level packaging structure 2 and a first passive component 3 , the fan-out wafer level packaging structure 2 and the first passive element 3 are provided with metal bumps 17 on the periphery, and the fan-out wafer level packaging structure 2, the first passive element 3 and the metal bump 17 are encapsulated There is a first molding compound 5, a chip 7 and a second passive component 8 are mounted on the back of the core interposer 1, and a second 3D conductive component 6 is arranged on the periphery of the chip 7 and the second passive component 8, and the chip 7. The second passive element 8 and the second 3D conductive component 6 are encapsulated with a second molding compound 9, the back of the second 3D conductive component 6 is provided with first solder balls 1...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a dual-side SiP three-dimensional package structure. The dual-side SiP three-directional package structure comprises a core pinboard (1), wherein a fan-out wafer-level packagestructure (2), a first passive component (3) and a first three-dimensional (3D) conductive part (4) are mounted on a front surface of the core pinboard (1), a chip (7), a second passive component (8)and a second 3D conductive part (6) are mounted on a back surface of the core pinboard (1), a first welding ball (10) is arranged on a back surface of the second 3D conductive part (6), shielding layers (15) are arranged on a front surface and a side surface of the package structure, and an opening (16) is formed in the shielding layer (15) on a front surface of the first 3D conductive part (4).By the dual-side SiP three-dimensional package structure, a pre-fabricated 3D conductive part can be used as a support structure for lamination and package, the 3D conductive part is used as a grounding end of electromagnetic shielding, the size height of a package module can be reduced, the high-frequency performance of the package module is improved, and electromagnetic interference is effectively prevented.

Description

technical field [0001] The invention relates to a double-sided SiP three-dimensional packaging structure, which belongs to the technical field of semiconductor packaging. Background technique [0002] According to the development of semiconductor technology, electronic devices have become miniaturized and lighter to meet users' needs, and thus, multi-chip packaging technology for realizing the same or different semiconductor chips from a single package has been enhanced. The multi-chip package is advantageous in terms of package size or weight and mounting process compared to a package realized by a semiconductor chip, and in particular, the multi-chip package is mainly applied to a portable communication terminal requiring miniaturization and weight reduction. [0003] However, with the high-density circuits in the packaging process, the use of various packaging materials, and the use of various chips and functional devices, the entire package is very complicated, and the m...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/538H01L23/48H01L23/552
CPCH01L23/538H01L23/552H01L23/48H01L2924/15311H01L2924/1533H01L2924/19105H01L2924/19106H01L2924/3025H01L2924/3511H01L2224/04105H01L2224/12105H01L2224/16225H01L2224/18H01L2224/24137
Inventor 林耀剑
Owner JCET GROUP CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com