A kind of manufacturing method of flash memory wafer

Abstract

The invention discloses a manufacturing method of a Flash wafer, comprising the following steps: S01: preparing a Flash wafer containing a storage area, a logic area and a capacitance area, and planarizing the upper surface thereof; S02: preparing the logic area and the capacitance area The height of the shallow trench filling silicon oxide in the region is adjusted; S03: Deposit a silicon nitride layer and a silicon oxide layer on the upper surface of the above-mentioned Flash wafer in sequence, and remove the upper surface of the storage region, the logic region and the upper surface of the floating gate of the capacitor region in sequence The silicon oxide layer and silicon nitride layer; S04: Adjust the height of the shallow trench filling silicon oxide in the storage area and the capacitor area to make it different; S05: Deposit an interlayer dielectric layer on the surface of the above-mentioned Flash wafer; S06: A photomask is used to protect the storage area and the capacitor area, and the remaining part of the logic area is removed to obtain the storage area, the logic area and the capacitor area with different heights of shallow trenches filled with silicon oxide. The invention can realize the independent adjustment of the height of silicon oxide filled in shallow trenches in the capacitor region.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a flash memory wafer. Background technique [0002] For flash memory products that use floating gates to store information, a capacitor region is usually added to the product. The film layer deposited on the newly added capacitance area is the same as the film layer of the control gate in the storage area, and there are floating gates above the active area in both the capacitance area and the storage area, and the floating gate is polysilicon. However, there is no floating gate on the shallow trench isolation in the capacitance area, and the width of the shallow trench isolation is larger than that in the storage area. Therefore, the subsequent process cannot control the polysilicon growth as in the storage region, so that the shallow trench isolation in the capacitor region is the same as the total thickness of the polysilicon layer on the a...

AI Technical Summary

Problems solved by technology

However, this change in the storage area will weaken the coupling ratio between the control gate and the floating gate, thereby affecting the storage performance of the product

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