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An anti-dpa attack method based on power equalization coding in aes circuit

A coding method and technology of power consumption, applied in the field of anti-DPA attack, to achieve the effect of simple chip manufacturing and convenient use

Active Publication Date: 2020-06-19
SOUTH CHINA UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the differential power analysis attack method, the attacker will generally first look for some attack points to attack. In these attack points, the circuit will generally directly operate the key, resulting in the power consumption information and key information leaked by the circuit. There is a great correlation between

Method used

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  • An anti-dpa attack method based on power equalization coding in aes circuit
  • An anti-dpa attack method based on power equalization coding in aes circuit
  • An anti-dpa attack method based on power equalization coding in aes circuit

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Embodiment

[0027] This embodiment provides an anti-DPA attack method based on power balance coding in an AES circuit. The method uses power balance coding technology to rebuild the wheel key addition module. The schematic diagram is as follows figure 1 shown, including the following steps:

[0028] Step 1. For the same binary data, design two sets of encoding methods: conventional power balance encoding and special power balance encoding respectively. Among them, binary data 00 corresponds to 0001 of conventional power balance encoding data, and corresponds to special power balance encoding data 1000; binary data 01 corresponds to 1101 of regular power balance coded data, and 0100 of special power balance coded data; binary data 10 corresponds to 1011 of regular power balance coded data, and corresponds to 0010 of special power balance coded data; The data 11 corresponds to 0111 of the conventional power balance coding data, and corresponds to 1110 of the special power consumption balanc...

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Abstract

The invention discloses a method for implementing DPA attack resistance based on power consumption balanced coding in an AES circuit. The method includes the following steps: 1, separately designing two sets of power consumption balanced coding methods that are regular coding and special coding for the same two-bit binary number; 2, converting each two-bit binary data in plaintext and key data into four-bit coded data, and storing the coded data in a register; 3, performing an XOR operation on two pieces of four-bit plaintext and key coded data and a constant 4'b0001, and storing a result in the register; and 4, in a register bank that stores the coded data, if the number of bits of data state changes in two pieces of continuously-input four-bit coded data is not two bits, enabling the second input data to perform switching between regular coding and special coding, and then storing the data in the register after conversion. In a circuit using the method, the register bank switches between regular coding and special coding to ensure that the leaked dynamic power consumption can be balanced, and thus the purpose of resisting DPA attacks can be achieved.

Description

technical field [0001] The invention relates to the fields of information security and digital integrated circuit design, in particular to an anti-DPA attack method based on power consumption equalization coding in an AES circuit. Background technique [0002] The AES algorithm is one of the most commonly used algorithms at present. As information security becomes more and more important in society, various encryption algorithms are widely proposed, such as DES (Data Encryption Standard, Data Encryption Standard), AES (Advanced Encryption Standard, Advanced Encryption Standard), ECC (Elliptic Curves Cryptography, elliptic curve cryptographic algorithm) and HASH (hash), etc. Among them, the AES algorithm has been widely used due to its high security. At present, the fastest supercomputer in the world cannot use the traversal method to crack the AES algorithm within an effective time. In some scenarios where a large amount of data needs to be processed, due to the complexity ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/06H04L9/00
CPCH04L9/003H04L9/0631H04L2209/12
Inventor 贺小勇吴镜聪荆朝霞
Owner SOUTH CHINA UNIV OF TECH