Thin film transistor, preparation method thereof, array substrate and display device

Abstract

The invention provides a thin film transistor, a preparation method thereof, an array substrate and a display device. The thin film transistor comprises a substrate, an active layer and a first source-drain electrode, wherein the active layer and the first source-drain electrode are arranged on the substrate. The first source-drain electrode is connected with the active layer. The first source-drain electrode in direct contact with the active layer is arranged, wherein a gate and the first source-drain electrode share the same thickness and material. Compared with the prior art, the thin filmtransistor has the advantages that an LDD region between the first source-drain electrode and the active layer is not needed; the total resistance between the source-drain electrode and the active layer no longer includes the resistance of the LDD region; and the resistance between the source-drain electrode and the active layer is effectively reduced. The first source-drain electrode can effectively shield side light, which can further improve the TFT illumination stability. Due to the fact that the gate and the first source-drain electrode share the same thickness and material, the gate andthe first source-drain electrode can be simultaneously formed. The preparation process is simplified. The yield is improved. The cost is reduced.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a thin film transistor, a preparation method thereof, an array substrate and a display device. Background technique [0002] In order to manufacture a display panel with a higher resolution, it is necessary to solve the problem of excessive parasitic capacitance of the TFT. In the prior art, a top-gate self-aligned TFT structure is generally used to reduce the parasitic capacitance of the TFT. However, the display panel with the top-gate TFT structure faces the following two problems to be solved. On the one hand, how to reduce the resistance between the active layer and the source-drain electrodes, refer to figure 1 , in order to reduce the contact resistance between the active layer and the source and drain, in the prior art, the area where the active layer 03 contacts the source and drain electrodes 02 is generally treated with gas plasma such as Ar and He, that is, the LDD i...

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Problems solved by technology

[0002] In order to produce a display panel with a higher resolution, it is necessary to solve the problem of excessive parasitic capacitance of the TFT. In the prior art, a top-gate self-aligned TFT structure is generally used to reduce the parasitic capacitance of the TFT.

However, the display panel with the top-gate TFT structure faces the following two problems to be solved. On the one hand, how to reduce the resistance between the active layer and the source-drain electrodes, refer to figure 1 , in order to reduce the contact resistance between the active layer and the source and drain, in the prior art, the area where the active layer 03 contacts the source and drain electrodes 02 is generally treated with gas plasma such as Ar and He, that is, the LDD is formed through a conductorization process ( Lightly Doped Drain (lightly doped drain structure) area 01, but the production of LDD area 01 has problems of complex process, low device mobility, and poor stability; on the other hand, because Oxide itself is sensitive to light, the channel under light The electrical characteristics of the area will change. In order to improve its light stability in the prior art, a layer of Shield layer 04 is usually made on the panel to play the role of blocking light. However, due to the existence of the LDD area 01, the Shield layer 04 cannot completely Effectively isolate the influence of light on the active layer 03, making TFT prone to Vth drift, and there is still the problem of poor light stability

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