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Method for legalizing overall layout of FPGA

A layout and overall technology, applied in the field of integrated circuit design, can solve the problems of not being able to connect the overall layout well, violating the overall layout, and large-scale movement of unit modules, so as to achieve the effects of easy expansion, improved efficiency, and reduced damage

Active Publication Date: 2018-04-27
SHANGHAI FUDAN MICROELECTRONICS GROUP
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Problems solved by technology

The quality of legalization has a great influence on the result of the layout, especially when there is a partially crowded area after the overall layout, unreasonable legalization can easily cause large-scale movement of unit modules, which violates the overall layout and cannot be well connected The result of the general layout

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  • Method for legalizing overall layout of FPGA
  • Method for legalizing overall layout of FPGA
  • Method for legalizing overall layout of FPGA

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Embodiment Construction

[0052] based on the following Figure 3 ~ Figure 8 , specifically explain the preferred embodiment of the present invention.

[0053] The legal layout plays a connecting role in the whole layout process, and it is the only way to convert the illegal layout into a legal layout. After the overall layout, the coordinates of the unit module are floating-point values, but the coordinates of the position (Site) on the chip where the unit can be placed are integer values. At this time, we need to round the coordinates of the unit module, similar to the branch definition. Processing operations. So in essence, legalizing the layout is an integer programming problem. However, if a general-purpose integer programming solver is used to solve it, the running time is not allowed. When the problem scale increases, the running time will increase exponentially.

[0054] Such as image 3 Shown, the present invention provides a kind of FPGA overall layout legalization method, comprises the f...

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Abstract

A method for legalizing the overall layout of an FPGA comprises the steps that firstly, an integer programming mode and a network flow mode are used for legalization of a macroblock; secondly, a constrained standard unit is legalized in a graded integer programming mode; finally, an unconstrained standard unit is legalized in a graded network flow mode. According to the method, by processing legalization of different types of unit modules with different constraints, legalization operation is conducted through small-range unit moving under the condition that an overall layout result is damagedas little as possible, and the effectiveness of the overall layout is guaranteed; the local congestion degree is reduced, so that damage of legalization to the overall layout is reduced; a legalized frame is very easy to expand through a graded mode, and the layout legalization efficiency is obviously improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) overall layout legalization method. Background technique [0002] FPGA adopts the concept of logic cell array LCA (Logic Cell Array), which includes configurable logic module CLB (Configurable Logic Block), input and output module IOB (Input Output Block) and internal wiring (Interconnect) and other parts. Field programmable gate array (FPGA) is a programmable device. Compared with traditional logic circuits and gate arrays (such as PAL programmable array logic, GAL gate array logic and CPLD complex programmable logic devices), FPGA has a different structure. FPGA uses a small look-up table (16×1RAM) to implement combinatorial logic, each look-up table is connected to the input of a D flip-flop, and the flip-flop drives other logic circuits or drives I / O, thus forming a combinatorial The logic functio...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 王似飞李佐渭沈磊翟四通吴昌
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP
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