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Transistors and methods of forming them

A transistor and gas flow technology, applied in transistors, semiconductor devices, electrical solid devices, etc., can solve the problems affecting transistor performance and parasitic capacitance, and achieve the effects of improving performance, reducing parasitic capacitance, and increasing distance

Active Publication Date: 2021-02-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The introduction of embedded silicon germanium technology or embedded silicon carbon technology can improve the carrier mobility of semiconductor devices to a certain extent, but in practical applications, it is found that the introduction of embedded silicon germanium technology or embedded silicon carbon technology can easily lead to High parasitic capacitance around transistor gate structures, affecting transistor performance

Method used

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  • Transistors and methods of forming them
  • Transistors and methods of forming them
  • Transistors and methods of forming them

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Experimental program
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Embodiment Construction

[0032] It can be seen from the background art that the performance of the transistors formed in the prior art is not good enough, and the reasons for the performance problems of a transistor are analyzed in combination with the formation process of a transistor.

[0033] Figure 1 to Figure 4 , shows a structural diagram corresponding to each step of a method for forming a transistor.

[0034] refer to figure 1 , providing the base. The base includes a substrate 10 and a plurality of fins 11 on the substrate 10 .

[0035] refer to figure 2 , figure 2 for in figure 1 Basically, it is a schematic diagram of a cross-sectional structure along the extending direction of the fin portion 11 . A gate structure 12 is formed across the fin portion 11 , and the gate structure 12 covers part of the top and sidewall surfaces of the fin portion 11 .

[0036] refer to image 3 , forming grooves 13 in the fins 11 on both sides of the gate structure 12 . The step of forming the groov...

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Abstract

A transistor and its forming method, the forming method comprising: providing a substrate; forming a gate structure on the substrate; forming grooves in the substrate on both sides of the gate structure; forming a first An epitaxial layer, the first epitaxial layer has doping ions; a mask layer is formed on the sidewalls on both sides of the gate structure, the mask layer is located on the first epitaxial layer and exposes a part of the first epitaxial layer An epitaxial layer surface; a second epitaxial layer is formed on the first epitaxial layer exposed by the mask layer, the second epitaxial layer has the same type of doping ions as the first epitaxial layer, and the first epitaxial layer has the same type of doping ions as the first epitaxial layer. Layers form source and drain doped regions. The forming method of the transistor provided by the present invention can reduce the parasitic capacitance between the source-drain doped region and the gate structure, thereby reducing the occurrence probability of signal delay phenomenon between semiconductor devices, and further improving the performance of the transistor.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique [0002] With the continuous development of semiconductor technology, carrier mobility enhancement technology has been widely studied and applied. Improving the carrier mobility in the channel region can increase the driving current of MOS devices and improve the performance of the devices. [0003] In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become an increasingly common means to improve the performance of MOS transistors through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, thereby increasing the driving current, thereby greatly improving the performance of MOS transistors. [0004]...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092H01L29/78
CPCH01L21/823814H01L21/823821H01L27/0924H01L29/785
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP