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Slope control circuit for erasing and writing voltage of non-volatile memory and non-volatile memory

A non-volatile memory and control circuit technology, applied in the field of electronics, can solve problems such as damage and failure of memory cells, and achieve the effect of improving efficiency

Active Publication Date: 2020-08-25
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to overcome the defect that the erasing and writing voltage of the storage unit in the prior art is not slope controlled, and the erasing and writing voltage is likely to cause damage to the SiO2 layer of the floating gate and cause the failure of the storage unit, and to provide a non-volatile Slope Control Circuit of Memory Erasing and Writing Voltage and Non-Volatile Memory

Method used

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  • Slope control circuit for erasing and writing voltage of non-volatile memory and non-volatile memory
  • Slope control circuit for erasing and writing voltage of non-volatile memory and non-volatile memory
  • Slope control circuit for erasing and writing voltage of non-volatile memory and non-volatile memory

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Experimental program
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Embodiment 1

[0041] Such as figure 2 As shown, the slope control circuit of the non-volatile memory erasing voltage involved in this embodiment, the slope control circuit 1 includes a charge pump 11, a charge pump clock control unit 12 and a detection unit 13, and the charge pump 11 is used to generate a target voltage VPP, the detection unit 13 is used to generate the detection voltage V from the target voltage VPP according to the received pulse clock signal CLK_PULSE det , the charge pump clock control unit 12 is used to detect the voltage V det Compared with the reference voltage VREF, the received charge pump clock signal CLK_PUMP is output to the clock input terminal CLKIN of the charge pump 11 according to the comparison result.

[0042] In specific implementation, the pulse clock signal CLK_PULSE is preferably a narrow pulse signal. Since the slope clock signal CLK_RAMP is generally a clock signal similar to a square wave, the pulse generating unit 14 can be used to generate the ...

Embodiment 2

[0057] Such as Figure 9 As shown, the nonvolatile memory involved in this embodiment includes the storage unit 2 and the slope control circuit 1 described in Embodiment 1, the output terminal of the charge pump 11 is electrically connected to the storage unit 2, and the target voltage VPP is used as the storage unit Erase and write voltage of cell 2. Here, the storage unit 2 is equivalent to the load capacitance C of the slope control circuit 1 load .

[0058] Thus, at power-up, the sense voltage V det The initial voltage is zero level, the output of the comparator 121 enables the first AND gate U1, so that the charge pump clock signal CLK_PUMP is output to the clock input terminal CLKIN of the charge pump 11, the charge pump 11 starts, the target voltage VPP rises, and passes the detection Capacitance C det making the detection voltage V det Follow the target voltage VPP to rise; when the detection voltage V det When rising to the reference voltage VREF, the output of th...

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Abstract

The invention discloses a slope control circuit of erase voltage of a nonvolatile memory and the nonvolatile memory, wherein the slope control circuit comprises a charge pump, a charge pump clock control unit and a detection unit; the charge pump is used for generating target voltage; the detection unit is used for producing the target voltage into detection voltage according to received pulse clock signals; and the charge pump clock control unit is used for comparing the detection voltage with reference voltage and outputs the received charge pump clock signals to a clock input end of the charge pump according to comparison results. The slope control circuit can control the rising slope of voltage by adjusting detection capacitance, reference voltage or the cycle of pulse clock signals, and the output of the charge pump does not have direct-current power consumption and has high efficiency.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a slope control circuit for rewriting voltage of a nonvolatile memory and a nonvolatile memory. Background technique [0002] In the existing NVM (Non-volatile Memory, non-volatile memory) structure, whether it is EEPROM (electrically erasable programmable read-write memory) or FLASH (flash memory), the storage unit is based on FOLTOX (Floating-gateTunnel Oxide, floating gate) structure, such as figure 1 As shown, the gate G, the drain D and the source S use FN (Flowler Nordheim) tunneling to charge and discharge the floating gate. During the process of cyclic erasing, the carriers pass through SiO2 (silicon dioxide) When the SiO2 layer enters the floating gate, the SiO2 layer will degrade and cause the NVM memory cell to eventually fail. The physical reason is that when electrons pass through SiO2, there is a certain probability of colliding with the internal lattice of SiO...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/12G11C16/30
CPCG11C16/12G11C16/30
Inventor 陈永耀刘耀平赵强
Owner SHANGHAI BEILING
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