Artificial neural network-based LRU Cache prefetching mechanism performance gain assessment method

Abstract

The invention discloses an artificial neural network-based LRU Cache prefetching mechanism performance gain assessment method. The method comprises the following steps of: selecting a neural network training parameter to fit an access stack distance distribution before the import of a prefetching mechanism and a Cache access missing frequency after the import of the prefetching mechanism, so as toconstruct a neural network model; calculating a target stack distance distribution of target programs; importing the calculated target stack distance distribution into the constructed neural model soas to predict Cache access missing frequencies of different target programs under the current prefetching mechanism; and calculating a Cache access missing frequency before the import of the prefetching mechanism by utilizing the stack distance distribution, and comparing the predicted Cache access missing frequencies under the current prefetching mechanism with the Cache access missing frequencybefore the import of the prefetching mechanism so as to assess performance gain of the prefetching mechanism. According to the method, the speed of predicting the performance gains of Cache prefetching mechanisms can be greatly enhanced.

Description

technical field [0001] The invention belongs to the technical field of computer architecture and modeling, and in particular relates to a method for evaluating the performance benefit of an LRU Cache prefetching mechanism based on an artificial neural network. Background technique [0002] Pre-silicon architecture evaluation and design space exploration based on hardware behavior modeling can provide guidance for chip design and reduce the iterative cycle of chip design. Under the modern processor architecture, the introduction of on-chip cache (Cache) can speed up memory access and improve CPU operating efficiency. However, the lack of Cache access will cause bubbles in the processor pipeline and even cause pipeline blockage, thereby reducing the computing performance of the processor. In order to improve the Cache access hit rate, the Cache design will introduce instruction or data prefetching to move the content that may be accessed in the future to the Cache in advance....

AI Technical Summary

Problems solved by technology

The disadvantage is that the obtained stack distance distribution can only reflect the characteristics of the memory access instruction flow at the software logic level, so the stack distance distribution cannot be directly applied to the Cache behavior modeling using the prefetch mechanism, but it can be used for Cache access before the prefetch mechanism is introduced. Missing count prediction

To put it simply, the prefetching mechanis

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