Semiconductor structure and formation method thereof

Abstract

The invention relates to a semiconductor structure and a formation method thereof. The method comprises steps that a substrate and separate fins on the substrate are provided; an isolation structure partially covering side walls of the fin portions is formed on the substrate; after forming the isolation structure, the pseudo gate structure crossing the fin portions and covering a part of top portions of the fin portions and side wall surfaces is formed; sidewalls are formed on the side walls of the pseudo gate structure; after forming the sidewalls, grooves are formed in the fins on both sidesof the pseudo gate structure; a doped epitaxial layer is formed in the grooves; after forming the doped epitaxial layer, an interlayer dielectric layer is formed on the isolation structure not covered by the pseudo gate structure, and the top portion of the pseudo gate structure is not covered by the interlayer dielectric layer; the pseudo gate structure is removed, and an opening is formed in the interlayer dielectric layer; a barrier layer is formed at the bottom of the opening; the barrier layer in the opening is removed; after removing the barrier layer, a metal layer is used for fillingthe opening to form the metal gate structure. The method is advantaged in that through the barrier layer, the doped epitaxial layer and the meal layer are isolated, and thereby the probability of bridging the metal gate structure and the doped epitaxial layer is reduced.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to accommodate the reduction in feature size, the channel length of MOSFETs has also been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur. [0003] Therefore, in order to better adapt to the reduction of the feature size, the semiconductor process gradu...

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Problems solved by technology

[0004] However, the electrical performance and yield of semiconduct

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