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Rework method for dual damascene through-hole technology

A through-hole process and process technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of reduced process effect, long process time, and low efficiency, so as to improve rework efficiency, improve rework quality, reduce The effect of steps

Active Publication Date: 2018-09-21
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0023] It can be seen from the above that in the existing rework process, the process of removing the three-layer structure is discontinuous, and three separate steps need to be carried out separately, which will make the process of removing the three-layer structure complicated, the process time is long, the efficiency is low, and the process effect will also reduce

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  • Rework method for dual damascene through-hole technology
  • Rework method for dual damascene through-hole technology
  • Rework method for dual damascene through-hole technology

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Embodiment Construction

[0052] Such as figure 2 Shown is the flow chart of the rework method of the double Damascus via process in the embodiment of the present invention; please refer to the device structure before the rework process figure 1 shown; as Figure 3A to Figure 3C As shown, it is a schematic diagram of the device structure in each sub-step of the rework method of the embodiment of the present invention. The rework method of the double damascene through-hole process of the embodiment of the present invention includes the following steps:

[0053] Step 1, such as figure 1As shown, the through hole of the double damascene passes through the first low-K dielectric layer 4, a second DARC layer 5 is formed on the first low-K dielectric layer 4, and a second DARC layer 5 is formed on the surface of the second DARC layer 5 A patterned third metal hard mask layer 7.

[0054] The mask structure defining the via holes includes a coating-based three-layer structure, the three-layer structure bei...

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Abstract

The invention discloses a rework method for a dual damascene through-hole technology. The method comprises the following steps that 1, a through hole of the damascene runs through a first low K dielectric layer, a second DARC layer is formed on the first low K dielectric layer, and a graphical third metal hard mask layer is formed on the surface of the second DARC layer; the second DARC layer withthe third metal hard mask layer is coated with a coating-based three-layer structure which is formed by overlaying an ODL layer, an SHB layer and a PR layer and used for defining the through hole; 2,lithography development of the through hole is performed; 3, detection is preformed after development is performed, after development is performed, when detection is out of the range, the rework technology of removing the three-layer structure is performed; in the rework technology, the PR layer, the SHB layer and the ODL layer are removed by adopting a dry etching technology and sequentially removed in the same dry etching equipment. Accordingly, the steps of the rework technology can be reduced, and the rework efficiency and quality are improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a rework method for a dual Damascene (DD) through-hole (VIA) process. Background technique [0002] Such as figure 1 As shown, it is a schematic diagram of the device structure after through-hole development in the existing double-damascus through-hole process; if an abnormality is found after through-hole development in the existing method, rework can be carried out. The steps of the existing rework process include: [0003] Step 1, such as figure 1 As shown, the through hole of the double damascene passes through the first low-K dielectric layer 4, and a second dielectric anti-reflection coating (DARC) layer 5 is formed on the first low-k dielectric layer 4, A patterned third metal hard mask layer 7 is formed on the surface of the second DARC layer 5 . [0004] The mask structure defining the through holes includes a coating-based three-layer s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/312H01L21/768
CPCH01L21/768
Inventor 李镇全
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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