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Testing method for single event effect of 3D (Three Dimensional) stacked storage

A single event effect, memory technology, applied in static memory, instruments, etc., can solve the problems of single event flip, ignore, read, write, and erase time, etc., to improve processing speed, prevent readback errors, Improve real-time effect

Inactive Publication Date: 2018-10-09
LANZHOU INST OF PHYSICS CHINESE ACADEMY OF SPACE TECH
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AI Technical Summary

Problems solved by technology

However, the storage device in the three-dimensional stacked package is different from the traditional two-dimensional packaged storage device in the way of single event effect when it encounters the impact of high-energy particles, and single event effect may occur in each layer.
[0004] Moreover, due to the larger storage capacity of memory devices in three-dimensional stacked packages, compared with single-layer memory, its reading, writing, and erasing time is relatively long, and in the process of reading, writing, and erasing, there may be single Particle Flip Condition
Therefore, just like the existing technology, only counting the single event upset in the case of static and dynamic reading, without considering the occurrence of the single event effect in the process of writing and erasing, it cannot meet the evaluation requirements of the single event effect test

Method used

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Embodiment Construction

[0034] The invention provides a single event effect test method for a 3D three-dimensional stacked memory, which includes four test modes, which are respectively a static mode, a dynamic read mode, a dynamic read / write mode and a dynamic read / erase / write mode; In each test mode, the memory to be tested with the initial data written is placed under the irradiation conditions of the simulated source in the laboratory, and the single particle irradiation test is carried out.

[0035] On the basis of the static mode and dynamic mode in the prior art, the present invention adds a dynamic read / write mode and a dynamic read / erase / write mode, and these two modes can count single event effects containing read / write operations occurrences, and single event effects involving read / erase / write operations. Through the comparison of the three dynamic modes, it is also possible to obtain the general situation of the single event effect that may occur in the process of writing alone and erasin...

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Abstract

The invention discloses a testing method for a single event effect of a 3D (Three Dimensional) stacked storage. The method comprises four test modes, including a static mode, a dynamic read mode, a dynamic read / write mode and a dynamic read / wipe / write mode. The method comprises the following steps: judging SEU in the static mode; judging SEL, SEU and SEFI in three dynamic modes; in the dynamic read / write mode, requiring to rewrite data after the SEU and the SEFI occur and before a continuous irradiation test is performed; in the dynamic read / wipe / write mode, wiping error cell data after the SEU and the SEFI occur and before the continuous irradiation test is performed and rewriting the data. By comparing the three dynamic modes, general conditions of the single event effect, which possiblyoccur in separately-write and separately-wipe process can be obtained, the consideration is more comprehensive and more accurate, data are provided for screening space applications of a high-capacitystorage device and reinforcing the single event effect.

Description

technical field [0001] The invention belongs to the technical field of space radiation effect testing, and in particular relates to a single event effect testing method for 3D three-dimensional stacked memories. Background technique [0002] With the development of microelectronics technology, the feature size of memory integrated circuits is gradually reduced. In advanced integrated circuits, the decreasing power supply voltage, higher and higher operating frequency, decreasing node capacitance and rapidly increasing chip complexity make the circuit more and more sensitive to the influence of the environment. When the integrated circuit is hit by high-energy particles in space, the circuit nodes will be charged and discharged instantaneously, which may destroy the internal state of the chip and cause the integrated circuit to have a transient failure, resulting in execution error or data error. [0003] With the continuous shrinking of transistors at the nanometer level, t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56
CPCG11C29/56004G11C29/56008G11C29/56016
Inventor 安恒薛玉雄杨生胜苗育君何熊宏张晨光王光毅乔佳
Owner LANZHOU INST OF PHYSICS CHINESE ACADEMY OF SPACE TECH
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