Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties
A threshold voltage and gate technology, applied in the fields of heterojunction field effect transistors or metal insulator semiconductors, can solve the problems of increasing device complexity and cost
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[0027] figure 1 A conventional HFET device 100 is shown. Substrate 102 is a crystalline semiconductor substrate, such as a silicon, silicon carbide, gallium nitride or sapphire wafer. The buffer layer 104 is typically formed of a crystalline III-V semiconductor material, such as a III-nitride material, such as GaN. It can be seen that the buffer layer 104 supports the channel 118 at an appropriate bias voltage. Barrier layer 106 is a different III-V semiconductor material with a wider bandgap than the material of buffer layer 104, and may be, for example, Al x Ga 1-x N, where x can vary, for example, from about 0.1 to about 1. Thus, barrier layer 106 and buffer layer 104 meet at heterojunction 108 . Both the buffer layer 104 and the barrier layer 106 are piezoelectric layers formed of a material having piezoelectric properties. Gate 110 is typically formed of a metal, such as a nickel bilayer or alloy, which will form a Schottky barrier with barrier layer 106 . Source 1...
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