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Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties

A threshold voltage and gate technology, applied in the fields of heterojunction field effect transistors or metal insulator semiconductors, can solve the problems of increasing device complexity and cost

Active Publication Date: 2018-10-23
SYNOPSYS INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Like other methods, additional deposition, etch, and cleaning steps are required, adding to device complexity and cost

Method used

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  • Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties
  • Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties
  • Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties

Examples

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Embodiment Construction

[0027] figure 1 A conventional HFET device 100 is shown. Substrate 102 is a crystalline semiconductor substrate, such as a silicon, silicon carbide, gallium nitride or sapphire wafer. The buffer layer 104 is typically formed of a crystalline III-V semiconductor material, such as a III-nitride material, such as GaN. It can be seen that the buffer layer 104 supports the channel 118 at an appropriate bias voltage. Barrier layer 106 is a different III-V semiconductor material with a wider bandgap than the material of buffer layer 104, and may be, for example, Al x Ga 1-x N, where x can vary, for example, from about 0.1 to about 1. Thus, barrier layer 106 and buffer layer 104 meet at heterojunction 108 . Both the buffer layer 104 and the barrier layer 106 are piezoelectric layers formed of a material having piezoelectric properties. Gate 110 is typically formed of a metal, such as a nickel bilayer or alloy, which will form a Schottky barrier with barrier layer 106 . Source 1...

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Abstract

Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

Description

Background technique [0001] The technology of the present invention involves heterojunction field effect transistors (HFETs) including high electron mobility transistors (HEMTs) or metal insulator semiconductor HFETs (MISHFETs) or dual-channel HFET / HEMT / MISHFET or dual-channel HFET / HEMT / MISHFET , or thin body (SOI, FinFET, Tri-Gate, Gate All Around, etc.) HFET / HEMT / MISHFET), which can be used as switching devices, for example. Such devices are typically formed from III-V semiconductors and achieve very high mobility by having an undoped channel region. In a conventional HFET, the device is described as "normally on," meaning that the threshold voltage (also known as the pinch-off voltage) is zero or negative, and the channel conducts current with little bias applied between the source and gate. with or without bias. For power electronics applications, normally-off devices are more preferred for reasons of safety, energy conversion and circuit design. For example, a normally...

Claims

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Application Information

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IPC IPC(8): H01L29/778H01L29/423G06F17/50H01L29/06
CPCH01L29/42316H01L29/42368H01L29/42376H01L29/7786H01L29/0657H01L29/2003G06F30/398G06F30/39G06F30/392G06F30/367H01L29/42364
Inventor H·Y·黄N·德阿尔梅达布拉加R·米克维科厄斯
Owner SYNOPSYS INC
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