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A Fault-Tolerant Memory Controller Supporting Above Note

A technology of memory controller and memory, which is applied in general stored program computers, instruments, architectures with a single central processing unit, etc., can solve problems that have not yet been discovered, and achieve significant scalability, good portability and reusability sexual effect

Active Publication Date: 2021-11-30
XIAN MICROELECTRONICS TECH INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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  • A Fault-Tolerant Memory Controller Supporting Above Note
  • A Fault-Tolerant Memory Controller Supporting Above Note

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Embodiment Construction

[0032] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0033] Such as figure 1 As shown, the fault-tolerant memory controller supporting the above note in the present invention is connected to the system bus inside the microprocessor chip, and transmits the memory access operation issued by the microprocessor through the standard on-chip bus. The signals transmitted by the standard on-chip bus include selection enable signals, access addresses, and read and write data.

[0034] The memory controller of the present invention includes a bus interface, a configuration register, a state machine, an encoder and a decoder, and two data PADs (PAD_DATA and PAD_EDAC). After the bus interface detects the effective access control signal, it will latch the address and data according to the bus protocol. There are two types of objects accessed by the bus, c...

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Abstract

The present invention provides a fault-tolerant memory controller that supports the above note. Based on the EDAC error correction and detection algorithm, the unified control mode of PROM and SRAM is decomposed into independent control modes of data domain and verification domain, thereby constructing an on-board micro-processing It is a mode in which the machine program runs and the verification element is executed in parallel. By adopting the strategy of combining the error correction and detection design structure with independently controllable configuration registers, the space program is realized, and the EDAC encoder and decoder for error correction and detection are integrated in the memory controller of the microprocessor. , adopting an independently controlled programming mode, the present invention has significant scalability, and it is not limited to the type, capacity, and quantity of off-chip memory, and can expand programming configuration registers to support more external memories, and has good portability Reusability and reusability constitute reusable IP for rapid design of SoC systems.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and relates to a fault-tolerant memory control technology suitable for space vehicle program registration, in particular to a fault-tolerant memory controller supporting registration. Background technique [0002] Thanks to the rapid development of microelectronics technology, integrated circuits are widely used in space vehicles to achieve their goals of miniaturization, multi-function and low power consumption. However, under the influence of the space radiation environment, space high-energy particles may cause the storage value in the integrated circuit memory to flip, resulting in wrong logical expression, affecting the normal function of the device, which is called single event flip. With the deepening of aerospace applications, aerospace electronic devices mostly use multi-mode redundancy, multi-machine backup, and error correction and detection technology (EDAC) for single event p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/78
CPCG06F15/7807G06F15/7817
Inventor 娄冕罗敏涛刘思源张海金田超
Owner XIAN MICROELECTRONICS TECH INST