A Fault-Tolerant Memory Controller Supporting Above Note
A technology of memory controller and memory, which is applied in general stored program computers, instruments, architectures with a single central processing unit, etc., can solve problems that have not yet been discovered, and achieve significant scalability, good portability and reusability sexual effect
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[0032] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.
[0033] Such as figure 1 As shown, the fault-tolerant memory controller supporting the above note in the present invention is connected to the system bus inside the microprocessor chip, and transmits the memory access operation issued by the microprocessor through the standard on-chip bus. The signals transmitted by the standard on-chip bus include selection enable signals, access addresses, and read and write data.
[0034] The memory controller of the present invention includes a bus interface, a configuration register, a state machine, an encoder and a decoder, and two data PADs (PAD_DATA and PAD_EDAC). After the bus interface detects the effective access control signal, it will latch the address and data according to the bus protocol. There are two types of objects accessed by the bus, c...
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