Metal gate manufacturing method

Abstract

The invention discloses a method for manufacturing a metal gate, comprising steps: step 1, forming a plurality of dummy gate structures on the surface of a semiconductor substrate, sidewalls flat with the surface of the dummy gate structures, a contact hole etching stop layer and layers Interlayer film; step 2, adjust and set the height of each dummy gate structure region according to the width of the dummy gate structure, the smaller the width of the dummy gate structure, the smaller the height of the dummy gate structure region, offset by reducing the height of the dummy gate structure region The impact of the reduction of the width of the dummy gate structure on the load increase of the metal chemical mechanical polishing process in the subsequent metal chemical mechanical polishing process of the metal gate makes the heights of the metal gates of various widths tend to be consistent after the metal chemical mechanical polishing process; step 3 1. Removing the dummy gate structure; step 4, performing metal deposition on the metal gate; step 5, performing a metal chemical mechanical polishing process to planarize the metal of the metal gate. The invention can stably control the height of the metal grid and improve the consistency of the height of the metal grid.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a metal gate. Background technique [0002] With the development of semiconductor technology, the advanced logic chip technology has reached the technology process below the 28nm node. In the process below 28nm, a metal gate with a high dielectric constant gate dielectric layer is usually used, usually abbreviated as HKMG, where HK represents a high dielectric constant (HK) gate dielectric layer, and MG represents a metal gate. [0003] In the formation process of HKMG, a dummy gate structure is usually required, and the dummy gate structure usually adopts a structure formed by stacking a gate dielectric layer such as a gate oxide layer and a polysilicon gate. After using the dummy gate structure to form components such as the source region, drain region, sidewall, contact hole etch stop layer (CESL) and interlayer film o...

AI Technical Summary

Problems solved by technology

[0009] The height difference of the metal grid will finally affect the characteristics of the original and make the characteristics of the original abnormal

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