A clock phase mismatch calibration circuit for multi-channel adc

Abstract

The invention provides a clock phase mismatch calibration circuit for multi-channel ADC, which belongs to the technical field of integrated circuits. The clock phase mismatch calibration circuit for multi-channel ADC includes a clock receiving circuit, a clock duty cycle stabilization circuit, a clock driving circuit, M delay circuits, M multi-phase clock generation circuits, and M clock equivalent delays The circuit, the N-bit analog-to-digital converter of the M channel, the reference clock generation circuit, the phase detector, the loop filter, the K-bit analog-to-digital converter and the control circuit can automatically trade off the calibration accuracy according to the system accuracy and hardware overhead, and Features low power consumption.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a clock phase mismatch calibration circuit for multi-channel ADC. Background technique [0002] The pipelined ADC (Analog-to-Digital Converter) with a precision of 14 bits and a sampling rate greater than 100MSPS has always been the main choice of various intermediate frequency sampling systems, so it is widely used in electronic application systems such as multi-carrier broadband wireless communication and radar reception. In order to reduce costs and improve reliability, various electronic systems have increasingly prominent requirements for low power consumption and miniaturization, and the requirements for power consumption and area of ​​ADC circuits used are increasingly stringent. In order to improve the integration level of the pipeline ADC, a single-chip integrated multi-channel ADC circuit is usually used to reduce the space occupied by the board-level system...

AI Technical Summary

Problems solved by technology

[0004] The object of the present invention is to provide a clock phase mismatch calibration circuit for multi-channel ADCs to solve the problems of delay and phase out-of-sync between existing ADCs

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