Flash memory preparation method
A flash memory and sacrificial layer technology, which is applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problem of unevenness on the surface of the mask layer, and achieve the effects of large selectivity, high etching selection ratio, and improved precision
Active Publication Date: 2018-11-13
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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[0004] The purpose of the present invention is to provide a preparation method of flash memory to solve the problem of unevenness on the surface of the mask layer in the prior art after the sidewall is formed by the etching process
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[0030] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. The advantages and features of the present invention will be more apparent from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
[0031] In the following description, it will be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being 'under' another layer, it can be directly under, and / or one or more intervening layers may also be present. In addition, designations regarding 'on' ...
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The invention provides a flash memory preparation method. The method includes the following steps: firstly, providing a front end structure, wherein the front end structure includes a first gate layer, a dielectric layer and a sacrificial layer that are formed in sequence; and then, performing first etching on the sacrificial layer; performing second etching on the sacrificial layer, forming a side wall in a first groove, and exposing the first gate layer, wherein the selectivity to the sacrificial layer during the second etching is greater than the selectivity to the sacrificial layer duringthe first etching. According to the flash memory preparation method, by adding an etching step, the etching process for forming the side wall is completed in two operations, and the selectivity to thesacrificial layer during the second etching is greater, the uniformity of etching is better, the selection ratio of etching is higher, so that after the etching process of the side wall is completed,the surface of the dielectric layer is no longer uneven, and the accuracy of the process can be improved. Thereby, the possible problems of performance degradation, reliability reduction, yield reduction and the like of the device can be solved.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a flash memory. Background technique [0002] In the manufacturing process of semiconductor devices, there are strict requirements for each step in the manufacturing process. Among them, etching is a process in which a specific part of the deposited layer is selectively removed by chemical means in the manufacture of semiconductor devices. Etching is critical to the electrical performance of semiconductor devices. If a mistake occurs during the etching process, it will cause the scrapping of the device which is difficult to recover, so strict process control must be carried out. [0003] In the current preparation process of the flash memory, when making the sidewall of the flash memory, a mask layer is generally formed on the gate layer first, wherein the mask layer has sidewall openings, and then the sidewall layer is formed on the mask layer. ...
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IPC IPC(8): H01L27/11521H10B41/30
CPCH10B41/30
Inventor 陈宏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP