Reconfigurable chip architecture for high-traffic network processing

Abstract

The invention discloses a reconfigurable chip architecture for high-traffic network processing. The reconfigurable chip architecture comprises an ingress policy module, a network message header processor and an egress policy module, wherein the ingress policy module slices a message, stores the message slices containing the payload of message data, and adds a corresponding storage address to the message header slices, and then assigns a sequence number to the message header slices, and assigns the message header slices carrying sequence number information to micro-engines with more idle threads; the network message header processor adopts multiple independent micro-engines to parse, classify and forward the received message header slices in parallel; the egress policy module parses a message header, extracts the payload of the message data from the cache, and splices the payload of the message data with the corresponding message header to form a complete message; and all messages are sequentially subjected to traffic shaping and queue management processing according to the sequence number of the message header, and then are divided into multiple paths and forwarded to an MAC module. The scheme of the invention has the advantages of flexibility, strong scalability and high processing speed.

Description

technical field [0001] The invention relates to a reconfigurable chip architecture for large-traffic network processing, belonging to the technical field of wired communication. Background technique [0002] With the commercialization of IP networks, especially after the emergence of Web technology, Internet users have increased rapidly. Network traffic, especially core network traffic, is growing exponentially. Traditional switches and routers based on high-performance CPUs can no longer meet the needs of network development, so ASICs have emerged to implement forwarding. It uses all the details of the forwarding process. implemented by hardware. ASIC technology solidifies instructions or calculation logic into hardware to obtain higher processing speed, so it can meet the performance requirements of switching and routing equipment and adapt to the growing trend of network traffic. However, the biggest disadvantage of ASIC technology is the lack of flexibility. Once the ...

AI Technical Summary

Problems solved by technology

[0003] The problem solved by the technology of the present invention is: to overcome the deficiencies of the prior art, to provide a reconfigurable chip architecture for large-traffic network processing, and to solve the poor flexibility and scalability of the switching chip implemented by the traditional OSI network architecture, Strong hardware dependence, long development cycle, high cost of replacement, unable to handle large network traffic data, inconvenient for structural adjustment, expansion and upgrade, etc.

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