Coprocessor, and method and system for matrix operation acceleration

A technology of co-processor and matrix operation, which is applied in the computer field and can solve problems such as poor computing power

Active Publication Date: 2018-11-20
SHENZHEN STATE MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In view of this, the embodiment of the present application provides a coprocessor, a matrix operation acceleration method and system to solve the problem of poor computing power of general-purpose microprocessors in the matrix operation process in the prior art

Method used

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  • Coprocessor, and method and system for matrix operation acceleration
  • Coprocessor, and method and system for matrix operation acceleration
  • Coprocessor, and method and system for matrix operation acceleration

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Embodiment 1

[0032] figure 1 A schematic structural diagram of the coprocessor provided by the embodiment of the present application is shown, as shown in figure 1 As shown, the co-processing 1 includes a controller 11, a register set 12, a MAC array 13 and a memory 14, wherein,

[0033] The controller 11 is connected to the MAC array 13 and the register set 12 respectively;

[0034] The register group 12 is also connected to the memory 14, and the group number of the register group 12 is greater than 1;

[0035] The coprocessor 1 communicates with the main processor 2 through an instruction channel. The interaction between the main processor 2 and the coprocessor 1 at the interface for transmitting instructions follows the coprocessing interface rules of the general processor.

[0036] The controller 11 is used to analyze the vector extension instruction received by the coprocessor 1, and is also used to call and send the data to be operated to the register group 12 according to the an...

Embodiment 2

[0053] In another embodiment provided by the present application, the MAC array includes m*n MACs, and the m*n MACs are arranged in a two-dimensional matrix structure to form the MAC array, where m and n are not less than 3 positive integer of .

[0054] Further, the arrangement structure of the register set is consistent with the arrangement structure of the MAC array, that is, it consists of m*n registers.

[0055] In this embodiment, each vector extension instruction parsed by the controller 11 includes a data transfer instruction and a matrix operation instruction. The data transfer instruction is used to instruct the register bank 12 to forward the data to be operated to the MAC array 13, and is also used to Instruct the register set 12 to forward the operation result of the MAC array 13 to the memory 14; the matrix operation instruction is used to instruct the MAC array 13 to perform a matrix operation on the received data to be processed, and the matrix operation instru...

Embodiment 3

[0068] Corresponding to the coprocessor described in the above embodiment, image 3 It shows the implementation flowchart of the matrix operation acceleration method provided by the embodiment of the present application, and the details are as follows:

[0069] The matrix operation acceleration method runs in the coprocessor provided in Embodiment 1 or Embodiment 2, including:

[0070] Step S31, receiving the vector extension instruction sent by the main processor through the instruction channel, analyzing the vector extension instruction, and obtaining an analysis result, wherein the vector extension instruction is generated by the main processor according to the data to be operated and a preset function;

[0071] In the embodiment provided by the present application, the coprocessor receives the vector extension instruction through the instruction channel, and after the coprocessor receives the vector extension instruction, the controller configured therein analyzes the vect...

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Abstract

The invention is applicable to the technical field of computers, and provides a coprocessor, and a method and a system for matrix operation acceleration. The coprocessor comprises a controller, a register bank, a multiplier-adder MAC array, and a memory. The controller parses a vector expansion instruction, and calls and sends data to be calculated to the register bank according to a parsing result. The register bank transmits the data to be calculated to the MAC array and transmits an operation result to the memory, the operation result being obtained by matrix operation of the MAC array on the data to be calculated, and the data to be calculated and/or the operation result are stored in the memory. In the process, the MAC array performs matrix operation according to the vector expansioninstruction, and the vector expansion instruction is generated by a main processor according to a preset function, ensuring computational power of a general microprocessor. The register bank transmitsand stores all kinds of data, and a data storage channel is independent of a receiving channel of the vector expansion instruction, improving data throughput of a general-purpose microprocessor in anoperation process.

Description

technical field [0001] The application belongs to the field of computer technology, and in particular relates to a coprocessor, a matrix operation acceleration method and a system. Background technique [0002] The development of technologies such as big data, cloud computing, and the Internet of Things will generate massive amounts of data that need to be processed. As a general data processing method, matrix computing, whether in the process of high-performance computing evaluation or in daily application algorithms, All play an important role. Due to the large amount of matrix operation data, it is often necessary to accelerate the operation process. Commonly used matrix operation acceleration processors include general-purpose microprocessors, digital signal processors (Digital Signal Processor, DSP), graphics processing units (Graphics Processing Unit, GPU) , application specific integrated circuit (Application Specific Integrated Circuit, ASIC) and field programmable ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/38G06F15/78
CPCG06F9/30014G06F9/30036G06F9/3877G06F15/7817G06F15/7867
Inventor 王文青谢文刚孙长江林涛陈岚
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
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