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A memory cell and a memory array and an OTP formed by the memory cell and the memory array

A technology of memory cells and drains, applied in the field of memory arrays and memory cells of one-time programmable read-only memory, can solve the problems of complicated wiring, unfavorable miniaturization, large area, etc., so as to improve the design margin and save the area. , the effect of halving the area

Inactive Publication Date: 2018-12-25
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] If the entire array is large, using the traditional OTP memory cell structure requires a large area, and the wiring will be more complicated, which is not conducive to miniaturization

Method used

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  • A memory cell and a memory array and an OTP formed by the memory cell and the memory array
  • A memory cell and a memory array and an OTP formed by the memory cell and the memory array
  • A memory cell and a memory array and an OTP formed by the memory cell and the memory array

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Embodiment Construction

[0079] Such as figure 2 As shown, the storage unit provided by the present invention is composed of an NMOS;

[0080] In programming mode, the gate of the NMOS is connected to a preset voltage, and the preset voltage is greater than or equal to the breakdown voltage of the NMOS.

[0081] In read mode, the NMOS drain is connected to 0V voltage, and the NMOS gate is connected to the circuit voltage.

[0082] If the measured NMOS gate-to-drain current value is less than the first threshold of 10 nanoampere-100 nanoamperes, it is judged that the memory cell has not been programmed; if the measured NMOS gate-to-drain current value is greater than the second threshold value of 0.1 mA -1mA judges that the memory cell is programmed. An unprogrammed memory cell represents a data 0, and a programmed memory cell represents a data 1.

[0083] Such as Figure 5 As shown, the present invention provides a storage array composed of the storage units, the storage array is an n...

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Abstract

The invention discloses a memory unit, which is composed of an NMOS. In a Programming mode, the NMOS drain is connected with a voltage of 0 V, and the NMOS gate is connected with a preset voltage; ina read mode, the NMOS drain is connected to 0V and the NMOS gate is connected to the circuit voltage. The invention also discloses a memory array composed of the memory cells. The invention also discloses an OTP, comprising: a power supply circuit is connected with a row address decoding circuit; a memory cell array is respectively connected with a row address decoding circuit, a column address decoding circuit and a high-speed current mode amplifier circuit; a supply circuit is connecte with a programming enable signal terminal, a row address decoding circuit is connecte with a read signal terminal, and a high-speed current-mode amplifier circuit is connected with that output terminal of the read-only memory. The memory array of the invention can save 50% of the array area and 33.3% of the winding complexity. The OTP of the invention can not only reduce the layout area but also increase the design margin.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a storage unit for a one-time programmable read-only memory. The present invention also relates to a storage array composed of the above storage units. And, an OTP (One Time Programmable Read Only Memory). Background technique [0002] Under the rapid development trend of the Internet of Things today, the Internet of Everything has begun to take shape. From shared bicycles to driverless cars; from smart watches to smart homes; devices will be interconnected with tens of billions or even hundreds of billions of other devices. Massive amounts of data will be stored in memory chips. Therefore, in the era of the Internet of Things, memory chips play a very important role. [0003] Non-volatile memory chip NVM (Non-Volatile Memory) ensures that the device can continue to store data after power failure, and is less affected by harsh environments, so it has a wide range of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C17/12
CPCG11C17/12
Inventor 龚政金建明顾明权力
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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