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Semiconductor device and method of forming the same

A semiconductor and device technology, applied in the field of semiconductor devices and their formation, can solve problems such as complex processes, and achieve the effect of simplifying the process and having good control ability.

Active Publication Date: 2020-10-30
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the process of forming semiconductor devices including N-type MOS transistors and P-type MOS transistors in the prior art is relatively complicated

Method used

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  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same

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Embodiment Construction

[0029] As mentioned in the background art, the process of forming semiconductor devices in the prior art is relatively complicated.

[0030] A method for forming a semiconductor device, comprising: providing a substrate, the substrate including a first region and a second region, the first region is used to form a P-type transistor, and the second region is used to form an N-type transistor; forming a first doped region and a second doped region, the first doped region is located in the first region of the substrate, and the second doped region is located in the second region of the substrate; the first metal silicide process is used to form the first metal silicide on the surface of the first doped region material layer; a second metal silicide layer is formed on the surface of the second doped region by a second metal silicide process, and the materials of the second metal silicide layer and the first metal silicide layer are different.

[0031] However, the above-mentioned ...

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Abstract

A semiconductor device and a method for forming the same are provided, the method comprising: a first region and a second region of a substrate corresponding to a second doped region having a first doped region and a blocked ion, respectively; forming a first metal layer on the surfaces of the first doped region and the second doped region; performing a first annealing so that the first metal layer reacts with the first source-drain doped region surface material and the second source-drain doped region surface material respectively to correspondingly form a first initial metal silicide layer and a second metal silicide layer with barrier ions; forming a second metal layer different from the first metal layer material on the surfaces of the first initial metal silicide layer and the secondmetal silicide layer; performing a second annealing at a temperature lower than that used for the first annealing, wherein atoms of the second metal layer diffuse to the first initial metal silicide layer to form a first metal silicide layer such that ions blocking ions block atoms of the second metal layer from diffusing into the second metal silicide layer. The method simplifies the process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] MOS transistors are one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and source and drain doped regions located in the semiconductor substrate on both sides of the gate structure. The working principle of the MOS transistor is: by applying a voltage to the gate structure, the current in the channel at the bottom of the gate structure is adjusted to generate a switching signal. [0003] The MOS transistors include N-type MOS transistors and P-type MOS transistors. The metal silicide on the surface of the source-drain doped region in the N-type MOS transistor needs to select a suitable material, so that the metal silicide o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092
CPCH01L21/8238H01L27/092
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP