Transconductance amplifier
A transconductance amplifier and amplifier technology, which is applied in the field of transconductance amplifiers, can solve the problems such as the large influence of the output signal settling time, and achieve the effects of improving the power supply suppression performance, improving the power supply suppression performance and increasing the stability.
Pending Publication Date: 2019-01-08
上海海栎创科技股份有限公司
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Problems solved by technology
[0010] This technique requires a large area of capacitance and has a greater impact on the output signal settling time
Method used
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[0029] The transconductance amplifier of the present invention will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.
[0030] In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of...
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A transconductance amplifier includes a first NMOS transistor, a second NMOS transistor, wherein the first NMOS transistor and the second NMOS transistor have a common source stage, a first PMOS transistor and a second PMOS transistor, wherein the first PMOS transistor and the second PMOS transistor have a common source stage and a common gate stage. The gate electrode of the first NMOS transistoris connected to the positive input terminal, the gate electrode of the second NMOS transistor is connected to a negative input terminal, the sources of the first NMOS transistor and the second NMOS transistor are connected to a current source, the drain of the first NMOS transistor is connected to one end of the first amplifier, the other end of the first amplifier is connected to the source of the second PMOS transistor, The drain of the second NMOS transistor is connected to one end of the second amplifier, the other end of the second amplifier is connected to the source of the first PMOS transistor, the drain of the first PMOS transistor is connected to one end of the third amplifier, the other end of the third amplifier is connected to the output end, and the drain of the second PMOStransistor is connected to the output end. The amplifier used in the invention adopts the structure of the current mirror amplifier, the gain of the noise at the gate control terminal and the power supply noise is close to 0 dB, and the output stage adopts the cascode structure, thus realizing good power supply rejection performance.
Description
technical field [0001] The invention relates to the field of integrated circuits, in particular to a transconductance amplifier. Background technique [0002] In order to improve the signal dynamic range of the transconductance amplifier as much as possible, on the one hand, traditional designs have developed various technologies to increase the signal output range, and on the other hand, various technologies have been developed to suppress power supply noise. Measured by the rejection ratio index, the higher the power supply rejection ratio, the higher the dynamic range of the signal. Traditional techniques for improving power supply rejection of transconductance amplifiers include the following: [0003] (1) Power pre-regulation technology; [0004] That is, the linear adjustment technology is used for the power supply, and the adjusted power supply is used to supply power to the transconductance amplifier, such as LDO (Low drop out) or sub-regulator (Sub-regulator). Th...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H03F3/45H03F1/56H03F1/26
CPCH03F1/26H03F1/56H03F3/45076H03F2203/45302
Inventor 王建军朱定飞刘华
Owner 上海海栎创科技股份有限公司