A power device and a manufacturing method thereof
A technology of power devices and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve problems such as increased input capacitance, increased switching loss, and extended switching time of devices
Inactive Publication Date: 2019-01-11
深圳市诚朗科技有限公司
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
The gate-to-drain capacitance directly affects the input capacitance and switching time of the device. The increase in the input capacitance will prolong the switching time of the device and increase the switching loss.
Method used
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[0049] The invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0050]It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.
[0051] If the purpose is to describe the situation directly on another layer or another ar...
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Abstract
The invention provides a power device and a manufacturing method thereof, comprising: growing a first epitaxial layer and a second epitaxial layer of the first conductivity type on an upper surface ofa substrate of the first conductivity type; Forming a first injection region of a second conductivity type within the first epitaxial layer; Forming a second injection region of a second conductivitytype within the second epitaxial layer; Forming a third injection region of a first conductivity type and a fourth injection region of a second conductivity type in the second injection region; Forming a first dielectric layer on an upper surface of the second implantation region; Forming a first polysilicon layer on an upper surface of the first dielectric layer; Forming a second dielectric layer on an upper surface of the second epitaxial layer; Forming a second polysilicon layer respectively connecting the first polysilicon layer and the first implanted region; Forming a source electrode on an upper surface of the second dielectric layer; Forming a gate connected to the second polysilicon layer within the second dielectric layer; a drain is formed on the lower surface of the substrate,and the power loss of the device is reduced.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a power device and a manufacturing method thereof. Background technique [0002] The drain and source poles of the vertical double diffused field effect transistor are on both sides of the device, so that the current flows vertically inside the device, which increases the current density, improves the rated current, and the on-resistance per unit area is also small. It is a very useful Wide range of power devices. The most important performance parameter of the vertical double-diffused field effect transistor is the operating loss, which can be divided into three parts: conduction loss, cut-off loss and switching loss. The conduction loss is determined by the conduction resistance, the cut-off loss is affected by the reverse leakage current, and the switching loss refers to the loss caused by the charging and discharging of parasitic capacitance during the switching proce...
Claims
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IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0623H01L29/66712H01L29/7804
Inventor 不公告发明人
Owner 深圳市诚朗科技有限公司