Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a manufacturing method thereof are provided. An exemplary semiconductor device may include a substrate including a base substrate, a first semiconductor layer on the base substrate, and a second semiconductor layer on the first semiconductor layer; First and second fin structures extending along the same straight line formed on the substrate, each fin structure comprising at least a second semiconductor layer; A first spacer formed around the first and second fin structures on both sides of the straight line; A first FinFET and a second FinFET formed on the substratebased on the first and second fin structures, respectively, wherein the first and second FinFETs include first and second gate stacks formed on the first isolation portion and intersecting with the first and second fin structures, respectively; And a second spacer intersecting the first and second fin structures between the first and second fin structures to isolate the first fin structure and the second fin structure from each other, wherein the second spacer extends parallel to at least one of the first and second gate stacks.

Description

technical field [0001] The present disclosure generally relates to the field of integrated circuit fabrication, and more particularly, to a semiconductor device including an isolation portion that can reduce area overhead and a fabrication method thereof. Background technique [0002] With the increasing demand for multifunctional, miniaturized electronic devices, it is expected to integrate more and more devices on a wafer. However, as current devices have been miniaturized to the physical limit, it is increasingly difficult to further reduce the average area per device. Additionally, any area overhead may result in increased manufacturing costs. [0003] One of solutions to meet the miniaturization trend is a three-dimensional device, such as a FinFET (Fin Field Effect Transistor). In FinFETs, the area occupied on the wafer surface is reduced by scaling in the height direction. However, compared to planar devices such as MOSFETs, the isolation between FinFETs takes up m...

AI Technical Summary

Problems solved by technology

However, compared to planar devices such as MOSFETs, the isolation between FinFETs takes up more area because each isolation requires two dummy gates.

In addition, the overlay accuracy of patterning or photolithography when forming isolation will also occupy the area and increase the manufacturing cost

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