MOS type power device and preparation method thereof

Abstract

The invention provides a MOS type power device and a preparation method thereof. A MOS-type power device comprises a substrate; a Well region; a Source region; a Gate oxide layer; a Gate electrode; anInsulating dielectric layer; A source region electrode, wherein a lower surface of the well region is provided with a protrusion extending downward. Thus, the MOS type power device has a well depth deep enough, sufficient withstand voltage margin can be ensured, At the same time, it has enough short channel and lower saturation voltage drop to increase channel density and reduce channel short-circuit current, effectively reduce on-resistance and improve short-circuit safety ability, fully ensure the reliability of device application, and has quasi-channel current self-pinch-off function to enhance the high-voltage and large-current shutdown ability of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a MOS type power device and a preparation method thereof. Background technique [0002] Saturation voltage drop and turn-off energy together constitute the "overall figure of merit (FOM)" to measure the performance of MOS power devices. However, the saturation voltage drop is greatly affected by the channel condition. The voltage drop across the channel is inversely proportional to the channel width and directly proportional to the channel length, so to reduce on-state power dissipation, the channel length should be as short as possible. But on the other hand, the channel length must be able to ensure the breakdown voltage, which limits the minimum allowable value of channel length reduction. In addition, the channel length also has the effect of limiting the short-circuit current, so as to avoid the device from being burned out in the case of a short-circuit of th...

AI Technical Summary

Problems solved by technology

[0009] However, the P-well region formed by the existing UMOS trench gate structure technology is a deep well planar junction. The characteristic of this well region is that the well depth and channel length cannot reach the optimal value at the same time.

In order to ensure sufficient withstand voltage of the device, the well depth should be at a minimum value, but the channel length cannot be optimized in this way.

And the deepe

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