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A GPU display memory management method with achain structure

A management method and chain technology, applied in image memory management, electrical digital data processing, processor architecture/configuration, etc., can solve the problems of low operation efficiency, low memory utilization, low security, etc., and improve security. , save memory resources and ensure the effect of efficiency

Inactive Publication Date: 2019-02-22
CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] In order to solve the problems of low video memory utilization, low operating efficiency, and low security in traditional methods, the purpose of the present invention is to provide a GPU video memory management method with a chain structure, which saves valuable video memory resources and improves program running speed and security. sex

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  • A GPU display memory management method with achain structure
  • A GPU display memory management method with achain structure
  • A GPU display memory management method with achain structure

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Embodiment Construction

[0036] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0037] The GPU video memory management method of a kind of chain structure shown in the present embodiment, aiming at the field of embedded systems, uses the heap (heap) object as the video memory management unit, based on the linked list structure, with "first adaptation" and "near idle" It is characterized by video memory management algorithms such as video memory block merging, and realizes video memory management functions such as video memory space initialization, video memory application, and video memory release.

[0038] Such as figure 1 As shown, the chain structure is composed of a heap object (heap object) and a video memory block (block). The block structure contains pointers to the actual video memory space. The forward third pointer and the backward fourth pointer enable the block to form a doubly linked list , each free block a...

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Abstract

The invention relates to a GPU display memory management method with a chain structure, comprising the following steps: 1) establishing heap objects in the GPU display memory space, wherein each heapobject is composed of at least one display memory block; and establishing a global linked list and an idle linked list; 2) when freeing the display memory space, marking the display memory block wherethe incoming address is located as idle, querying whether the front and back display memory blocks of the current display memory block are idle display memory blocks, if so, performing merging, and updating the global link list and the idle link list. The invention adopts a merging algorithm of adjacent idle blocks, which ensures the efficiency, reduces the generation of display memory fragmentsand improves the use efficiency of the display memory.

Description

technical field [0001] The invention belongs to the field of graphics processor drivers, and relates to a method for managing on-chip video memory on a GPU chip. Background technique [0002] Graphics processing units (GPUs) are widely used in various fields that require graphics generation and display, such as industry, medical care, and consumer electronics. The most common application scenario is that the central processing unit (CPU) interacts with the GPU through the PCI or PCIE bus for data and commands. , the GPU is responsible for drawing graphics and outputting them. In the process of 3D graphics generation, a large amount of data needs to be moved from the CPU local memory to the GPU or from the GPU to the CPU memory. Limited by memory bandwidth and PCI / PCIE bus bandwidth, the speed at which the GPU reads and writes data from the CPU local memory Far lower than the speed at which the GPU can read and write data from the on-chip video memory. Taking the commonly us...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06T1/20G06T1/60
CPCG06F9/5016G06F9/5061G06F2209/5012G06T1/20G06T1/60
Inventor 廖科时洋洋李少光
Owner CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST