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Semiconductor structures and methods of forming them

A technology of semiconductor and gate structure, applied in the field of semiconductor structure and its formation, can solve the problem that the electrical performance and yield rate of semiconductor devices need to be improved, and achieve the effect of improving production yield rate and device performance and avoiding leakage current.

Active Publication Date: 2021-11-12
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the electrical performance and yield of semiconductor devices composed of planar MOS transistors or fin field effect transistors still need to be improved.

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Experimental program
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Embodiment Construction

[0028] As mentioned in the background art, with the increase in density and the reduction in size of semiconductor devices, the electrical performance of semiconductor devices still needs to be improved. Since the size of the semiconductor device is smaller, the distance between the gate and the source-drain doped regions in the device is closer, the risk of short circuit is greater, and the impact on the reliability of the device is more obvious. It will be described below in conjunction with the accompanying drawings.

[0029] Figure 1 to Figure 4 It is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0030] Please refer to figure 1 , provide a substrate 100, the substrate has a fin 101 and an isolation structure 102, the isolation structure 102 covers part of the sidewall of the fin 101; a dummy gate oxide film 110 is formed on the surface of the substrate 100, and the A dummy gate layer 112 is formed on the dummy gate oxi...

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Abstract

The present invention provides a semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate with a dummy gate structure on the substrate, and the dummy gate structure includes: a dummy gate oxide layer located on the dummy gate oxide layer The dummy gate layer and the first sidewall, the first sidewall is located on the sidewall of the dummy gate layer; the second sidewall is formed on the sidewall of the dummy gate structure; in the dummy gate structure Forming a source-drain doped region in the semiconductor substrate on both sides of the second sidewall; after forming the source-drain doped region, forming a dielectric layer on the semiconductor substrate, the dielectric layer covering the second sidewall; removing The dummy gate layer and the dummy gate oxide layer form an opening in the dielectric layer; a gate structure is formed in the opening. The present invention uses the second sidewall to isolate the source-drain doped region from the gate structure, thereby reducing the probability of short circuit between the gate structure and the source-drain doped region.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. The gate size of planar transistors is getting smaller and smaller, so the gate's ability to control the channel current becomes weaker. It is easy to produce short channel effect, causing leakage current problems, and then affecting the electrical performance of semiconductor devices. [0003] In order to further reduce the size of the device and increase the density of the device, a high-k metal gate transistor is introduced on the basis of the fin field effect transistor, that is, a high-k dielectric material is used as the gate dielectric layer, and a metal material is used as the gate. The high-K metal gate t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
CPCH01L29/6681
Inventor 张焕云吴健
Owner SEMICON MFG INT (SHANGHAI) CORP