Optimization method of random vibration stress and return loss of chip package solder joints

Abstract

The invention discloses an optimization method for improving random vibration stress and echo loss of chip package solder joints by unilaterally performing vibration analysis research or unilateral echo loss research. CSP solder joint models are established in ANSYS and HFSS software, the finite element analysis model and three-dimensional electromagnetic simulation analysis of the model are carried out, Response surface method is used to design the horizontal combination of multi-group solder joint morphology parameters and to model for simulation calculation, and the response surface methodis used to calculate the stress value, the relationship between the return loss and the shape parameters of CSP solder joints is fitted, The initial population generation, crossover, mutation and evolutionary inversion were performed on the fitting function respectively, and the two populations were evaluated and updated as a whole. The local catastrophe is performed on the population if the conditions were satisfied, and the random vibration stress value and echo loss value of CSP solder joints were obtained while the parameter level combination is reduced. This method can be used to guide the design of structural parameters which take into account the random vibration stress and return loss of CSP solder joints.

Description

technical field [0001] The invention relates to the technical field of microelectronic packaging reliability and signal integrity, in particular to a method for optimizing random vibration stress and return loss of chip packaging solder joints based on response surface and genetic algorithm. Background technique [0002] With the rapid development of automotive electronic devices and other consumer electronics products, microelectronic packaging technology is facing the challenges and opportunities of "miniaturization, multi-function, high integration and low cost". Chip Scale Package (CSP) technology developed on the basis of QFP (Quad Flat Package) and TQFP (Plastic Quad Flat Package) can ensure high-performance, high-reliability large-scale integrated circuits Under the premise of achieving the smallest package size of the chip, the relative cost is lower. Compared with the ball grid array (Ball grid array, CSP) packaging technology, the area occupied by the printed board...

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Problems solved by technology

[0010] In the above two documents, the influence of the size parameters of solder joints on the return loss of solder joints was studied, but the existing research results reflect that domestic and foreign scholars are limited to unilateral vibration analysis or unilateral vibration analysis of solder joints. The study of signal integrity does not take into account the vibration analysis an

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