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A method for heat management in SOP system integration

A management method and system integration technology, applied in the field of SOP packaging, can solve the problems of overheating of 3D stacked chips, increase of total power, expensive thermal management system, etc., and achieve the effect of reducing chip temperature, improving overheating, and optimal thermal management scheme

Active Publication Date: 2019-03-08
TAICANG T&W ELECTRONICS CO LTD
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AI Technical Summary

Problems solved by technology

Because SOPs generate a lot of heat when they work or it is too expensive to build a thermal management system, thermal management has become an obstacle to the development of SOPs. The reasons are: (1) the heat flux generated by stacked multifunctional chips in micro-packages is very high, (2) ) The 3D circuit increases the total power per unit area, (3) If there is no effective and sufficient cooling treatment, it will cause overheating of the 3D stacked chips, (4) the space between the 3D stacked chips is too small for the cooling channel, For example, there is no gap for fluid flow, (5) thin chips can cause hot spots on the chip

Method used

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  • A method for heat management in SOP system integration
  • A method for heat management in SOP system integration
  • A method for heat management in SOP system integration

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Embodiment Construction

[0021] The present invention is described in further detail below in conjunction with accompanying drawing:

[0022] When n-layer chips are stacked, the highest layer is the farthest from the heat sink, so the temperature is the highest, and for the current mature SOP technology, there is an urgent need for low-cost, high-efficiency thermal management design guidelines and solutions, and the present invention is here Based on the temperature analysis model proposed on the basis, TSV (Through Silicon Via) technology is the core of 3D IC integration, and it is also an important supporting technology. It can effectively reduce the temperature of the chip to a certain extent, so the present invention first considers when there is no TSV. The temperature analysis model of the n-layer chip, based on which a one-dimensional thermal analysis model is deduced, and then the temperature of the highest layer chip is deduced. In the chip stack, the higher the number of layers, the more diff...

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Abstract

A method for heat management in SOP system integration is provided. A through-silicon via is provided in that multilayer stacked chip, and a heat conduction model of the multilayer stacked chip with silicon vias is established, the invention utilizes matlab and ansys icepeak to compare and verify the simulation results, and then determines the size and quantity of the through silicon holes. The invention solves the problem of overheating by using TSV in the SOP system integration, determines the number and size of TSV through simulation, and realizes the optimal thermal management scheme.

Description

technical field [0001] The invention belongs to the technical field of SOP packaging, and in particular relates to a thermal management method in SOP system integration. Background technique [0002] SOP (system on package) system-in-package is an emerging system-in-package system with the characteristics of miniaturization, low cost, high functional integration, and high reliability. Therefore, SOP has broad prospects in packaging technology. Because SOPs generate a lot of heat when they work or it is too expensive to build a thermal management system, thermal management has become an obstacle to the development of SOPs. The reasons are: (1) the heat flux generated by stacked multifunctional chips in micro-packages is very high, (2) ) The 3D circuit increases the total power per unit area, (3) if there is no effective and sufficient cooling treatment, it will cause overheating of the 3D stacked chips, (4) the space between the 3D stacked chips is too small for the cooling c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F2119/08G06F30/23G06F30/39G06F30/20Y02D10/00
Inventor 王瑞
Owner TAICANG T&W ELECTRONICS CO LTD
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